SPRADQ5 March   2025 AM2612 , AM2612-Q1 , AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1 , AM263P2-Q1 , AM263P4 , AM263P4-Q1

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction of AC or Servo Drive Hot-Side Control Architecture
  5. 2PRU and FSI Implementation for Time Synchronization and Data Transmitting
    1. 2.1 Importance of Clock in Industrial Systems With MCUs
    2. 2.2 IEP Timer Interface
    3. 2.3 PRU_ICSSG Task Manger
    4. 2.4 Fast Serial Interface
    5. 2.5 Two-Chip System Scheme for Time Synchronization and Data Transmitting
      1. 2.5.1 Device 1 Configuration
        1. 2.5.1.1 Pad Configuration
        2. 2.5.1.2 Clock Source Configuration
        3. 2.5.1.3 IEP Timer Configuration
        4. 2.5.1.4 Task Manager Configuration
      2. 2.5.2 Device 2 Configuration
        1. 2.5.2.1 Pad Configuration
        2. 2.5.2.2 Clock Configuration
        3. 2.5.2.3 IEP Timer Configuration
        4. 2.5.2.4 TSR Configuration
        5. 2.5.2.5 Task Manager Configuration
  6. 3Verification
  7. 4Summary
  8. 5References

2.3 PRU_ICSSG Task Manger

The dedicated task manager is integrated for each PRU core of the PRU_ICSSG system used for efficient switching between tasks. Each task manager works independently from the others. The task manager has two modes of operation that are general purpose mode and RX_TX mode for Ethernet purpose.

In this application, general purpose mode is used to improve the firmware efficiency and performance. This feature enables software to get preempted to do another higher priority task. The task manager can issue the hardware preemption and respond to the relative instruction by saving off the current program counter and flags and providing a new program counter (PC) to start a new task. When the firmware completes this new task, the firmware can terminate this task by issuing a dedicated instruction. When the task manager sees this execution of this instruction, the task manager can return the state of the PRU from the last saved off task. This hardware context switching block diagram is shown on Figure 2-3. The firmware is responsible for saving and restoring any internal registers that the firmware can override during a task. The data RAM or shared RAM can be used to store the register value. The multi tasks can be mapped and triggered by source event such as IEP compare event, IEP capture event and interrupt controller (INTC) host event so that all the tasks timing is deterministic and pre-configured.

PRU_ICSSG Task Manager Hardware Context Switching Block DiagramFigure 2-3 PRU_ICSSG Task Manager Hardware Context Switching Block Diagram