SPRADQ5 March   2025 AM2612 , AM2612-Q1 , AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1 , AM263P2-Q1 , AM263P4 , AM263P4-Q1

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction of AC or Servo Drive Hot-Side Control Architecture
  5. 2PRU and FSI Implementation for Time Synchronization and Data Transmitting
    1. 2.1 Importance of Clock in Industrial Systems With MCUs
    2. 2.2 IEP Timer Interface
    3. 2.3 PRU_ICSSG Task Manger
    4. 2.4 Fast Serial Interface
    5. 2.5 Two-Chip System Scheme for Time Synchronization and Data Transmitting
      1. 2.5.1 Device 1 Configuration
        1. 2.5.1.1 Pad Configuration
        2. 2.5.1.2 Clock Source Configuration
        3. 2.5.1.3 IEP Timer Configuration
        4. 2.5.1.4 Task Manager Configuration
      2. 2.5.2 Device 2 Configuration
        1. 2.5.2.1 Pad Configuration
        2. 2.5.2.2 Clock Configuration
        3. 2.5.2.3 IEP Timer Configuration
        4. 2.5.2.4 TSR Configuration
        5. 2.5.2.5 Task Manager Configuration
  6. 3Verification
  7. 4Summary
  8. 5References

2.5.2.3 IEP Timer Configuration

The compare event and SYNC0 configuration is the same as device 1, with the following additional steps. Enable capture 6 event CAP6 by setting bit 6 in the IEP_CAP_CFG_REG register (0x3002E018). The IEP counter value is captured to CAP6 register when a latch event occurs due to the sync signal from device 1. This is achieved by routing the sync signal from device 1 through the PRG0_PRU0_GPO18 to the IEP latch of device 2 using the TSR module.