SPRADQ5 March   2025 AM2612 , AM2612-Q1 , AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1 , AM263P2-Q1 , AM263P4 , AM263P4-Q1

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction of AC or Servo Drive Hot-Side Control Architecture
  5. 2PRU and FSI Implementation for Time Synchronization and Data Transmitting
    1. 2.1 Importance of Clock in Industrial Systems With MCUs
    2. 2.2 IEP Timer Interface
    3. 2.3 PRU_ICSSG Task Manger
    4. 2.4 Fast Serial Interface
    5. 2.5 Two-Chip System Scheme for Time Synchronization and Data Transmitting
      1. 2.5.1 Device 1 Configuration
        1. 2.5.1.1 Pad Configuration
        2. 2.5.1.2 Clock Source Configuration
        3. 2.5.1.3 IEP Timer Configuration
        4. 2.5.1.4 Task Manager Configuration
      2. 2.5.2 Device 2 Configuration
        1. 2.5.2.1 Pad Configuration
        2. 2.5.2.2 Clock Configuration
        3. 2.5.2.3 IEP Timer Configuration
        4. 2.5.2.4 TSR Configuration
        5. 2.5.2.5 Task Manager Configuration
  6. 3Verification
  7. 4Summary
  8. 5References

2.5.1.3 IEP Timer Configuration

The IEP counter value can be read from the IEP_COUNT_REG0 (0x3002E010) and IEP_COUNT_REG1 (0x3002E014) registers. A compare event (CMP0 event) is generated when the IEP counter reaches the compare value set in CMP0 register.

Set the IEP counter to wrap around when the counter reaches the CMP0 value. To achieve this, set CMP0_RST_CNT_EN bit field = 0x1 in IEP_CMP_CFG_REG register (0x3002E070) register and enable CMP0 event.

Configure CMP0_0 bit field = 62500 - 4 in the IEP_CMP0_REG0 register (0x3002E078), resulting the IEP counter resets every 62500 counts, which corresponds to 62.5µs when the IEP clock source runs at 250MHz and the IEP counter is incremented by four per clock cycle.

Configure CMP1_0 bit field = 1000 - 4 in the IEP_CMP1_REG0 register (0x3002E080), to define the activation time of the sync signal to 1µs, which defines at which point in IEP counter the sync signal is activated, and enable CMP1 event.

Set the IEP counter’s default increment value by configuring the DEFAULT_INC bit field = 0x4 in IEP_GLOBAL_CFG_REG register (0x3002E000), resulting the IEP counter increments four times per IEP source clock cycle.

Define the SYNC0 pulse width as 10 clock cycles by writing SYNC_HPW bit field = 10 - 1 in the IEP_SYNC_PWIDTH_REG register (0x3002E190). This determines the duration for which SYNC0 signal remains high.

Set SYNC_EN and SYNC0_EN bit fields = 0x1 and SYNC0_CYCLIC_EN bit field = 0x0 in the IEP_SYNC_CTRL_REG (0x3002E180) register to enable SYNC0 in single-shot mode.

Set the PWM_EFC_EN bit field = 0x1 in the ICSSG_SA_MX_REG register (0x30026040) to enable the IEP CMP flags to get auto hardware cleared.

Once the required register configurations are done, the CMP0 task is written.