STDA017 November   2025 TPS7A33 , TPS7A4501-SP , TPS7A47 , TPS7A47-Q1 , TPS7A4701-EP , TPS7A52 , TPS7A52-Q1 , TPS7A53 , TPS7A53-Q1 , TPS7A53A-Q1 , TPS7A53B , TPS7A54 , TPS7A54-Q1 , TPS7A57 , TPS7A8300 , TPS7A83A , TPS7A84 , TPS7A84A , TPS7A85A , TPS7A90 , TPS7A91 , TPS7A92 , TPS7A94 , TPS7A96 , TPS7B7702-Q1 , TPS7H1111-SEP , TPS7H1111-SP

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction to Parallel LDOs Using Ballast Resistors
  5. 2Noise Analysis of Parallel LDOs Using Ballast Resistors
  6. 3LDO Output Impedance
  7. 4Strategies on Reducing the Noise of the Parallel LDO System
  8. 5Noise of Parallel LDOs Using Ballast Resistors
    1. 5.1 TPS7A57
    2. 5.2 TPS7A94
  9. 6Noise Measurements of Alternative Parallel LDO Architectures
    1. 6.1 TPS7B7702-Q1
  10. 7Conclusion
  11. 8References

TPS7B7702-Q1

The TPS7B7702-Q1 [7] is a dual linear regulator with diagnostic features commonly used in standalone or in parallel applications. Ballast resistors can be used to parallel the TPS7B7702-Q1 (see Figure 6-1), and when using this architecture, the noise decreases with the √n (see Figure 6-2). See the reference design for test data covering the parallel operation using ballast resistors and op-amps [10]. Both channels inside the TPS7B7702-Q1 share the same VIN pin, so a modified schematic to achieve similar paralleled LDOs is used in [10] (see Figure 6-3 below).

TPS7A94 TPS7A96 TPS7A57 TPS7B7702-Q1 Parallel TPS7B7702-Q1 Using
                    Op-Amps Figure 6-3 Parallel TPS7B7702-Q1 Using Op-Amps

The noise performance for three parallel LDO topologies was evaluated using the TPS7B7702‑Q1 LDO:

  1. Op‑amp‑controlled architecture – A single primary LDO channel drives up to three secondary LDO channels through external operational amplifiers.
  2. Current‑mirror architecture – Two TPS7B7702‑Q1 channels are paralleled using a current‑mirror network (see Figure 6-3).
  3. Ballast‑resistor architecture – Two TPS7B7702‑Q1 channels are paralleled with discrete ballast resistors placed at each output of the regulator.

Noise was measured at the output of the parallel LDOs for each topology. The current‑mirror and ballast‑resistor configurations were tested with two parallel LDO channels; whereas, the op‑amp‑controlled architecture was evaluated with up to four parallel LDO channels (one primary, plus three secondaries).

All configurations produced output‑noise levels equal to or higher than the noise of a single TPS7B7702‑Q1, except for the ballast‑resistor method. Only the ballast‑resistor topology achieved a measurable reduction in noise, confirming the theoretical prediction presented earlier in this white paper (see Figure 6-4).

TPS7A94 TPS7A96 TPS7A57 TPS7B7702-Q1 Only the Ballast Resistor
                    Technique Offers Reduced System Noise Figure 6-4 Only the Ballast Resistor Technique Offers Reduced System Noise