DLPS292 July   2025 DLPC8424 , DLPC8444 , DLPC8454

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Compatability Table
  6. 5 Pin Configuration and Functions
    1.     7
    2. 5.1  Initialization, Board Level Test, and Debug
    3. 5.2  V-by-One Interface Input Data and Control
    4. 5.3  FPD-Link Port(s) Input Data and Control
    5. 5.4  DSI Input Data and Clock (Not Supported in DLPC8424, DLPC8444, and DLPC8454)
    6. 5.5  DMD SubLVDS Interface
    7. 5.6  DMD Reset and Low-Speed Interfaces
    8. 5.7  Flash Interface
    9. 5.8  Peripheral Interfaces
    10. 5.9  GPIO Peripheral Interface
    11. 5.10 Clock and PLL Support
    12. 5.11 Power and Ground
    13. 5.12 I/O Type Subscript Definition
    14. 5.13 Internal Pullup and Pulldown Characteristics
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2.     23
    3. 6.2  ESD Ratings
    4. 6.3  Recommended Operating Conditions
    5. 6.4  Thermal Information
    6. 6.5  Power Electrical Characteristics
    7. 6.6  Pin Electrical Characteristics
    8. 6.7  DMD SubLVDS Interface Electrical Characteristics
    9.     30
    10. 6.8  DMD Low-Speed Interface Electrical Characteristics
    11.     32
    12. 6.9  V-by-One Interface Electrical Characteristics
    13. 6.10 FPD Link LVDS Electrical Characteristics
    14. 6.11 USB Electrical Characteristics
    15.     36
    16. 6.12 System Oscillator Timing Requirements
    17.     38
    18. 6.13 Power Supply and Reset Timing Requirements
    19.     40
    20. 6.14 V-by-One Interface General Timing Requirements
    21.     42
    22. 6.15 FPD Link Interface General Timing Requirements
    23. 6.16 Flash Interface Timing Requirements
    24.     45
    25. 6.17 Source Frame Timing Requirements
    26.     47
    27. 6.18 Synchronous Serial Port Interface Timing Requirements
    28.     49
    29. 6.19 I2C Interface Timing Requirements
    30. 6.20 Programmable Output Clock Timing Requirements
    31. 6.21 JTAG Boundary Scan Interface Timing Requirements (Debug Only)
    32.     53
    33. 6.22 DMD Low-Speed Interface Timing Requirements
    34.     55
    35. 6.23 DMD SubLVDS Interface Timing Requirements
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagrams
    3. 7.3 Feature Description
      1. 7.3.1 Input Sources
      2. 7.3.2 V-by-One Interface
      3. 7.3.3 FPD-Link Interface
      4. 7.3.4 DMD (SubLVDS) Interface
      5. 7.3.5 Serial Flash Interface
      6. 7.3.6 GPIO Supported Functionality
        1.       67
        2.       68
      7. 7.3.7 Debug Support
  9. 8 Power Supply Recommendations
    1. 8.1 System Power-Up and Power-Down Sequence
    2. 8.2 DMD Fast Park Control (PARKZ)
    3. 8.3 Power Supply Management
    4. 8.4 Hotplug Usage
    5. 8.5 Power Supplies for Unused Input Source Interfaces
    6. 8.6 Power Supplies
      1. 8.6.1 Power Supplies DLPA3085 or DLPA3082
  10. 9 Layout
    1. 9.1 Layout Guidelines
      1. 9.1.1 Layout Guideline for DLPC8424 or DLPC8444 or DLPC8454 Reference Clock
        1. 9.1.1.1 Recommended Crystal Oscillator Configuration
      2. 9.1.2 V-by-One Interface Layout Considerations
      3. 9.1.3 DMD Maximum Pin-to-Pin, PCB Interconnects Etch Lengths
      4. 9.1.4 Power Supply Layout Guidelines
    2. 9.2 Thermal Considerations
  11. 10Device and Documentation Support
    1. 10.1 Third-Party Products Disclaimer
    2. 10.2 Documentation Support
      1. 10.2.1 Related Documentation
    3. 10.3 Receiving Notification of Documentation Updates
    4. 10.4 Support Resources
    5. 10.5 Device Nomenclature
      1. 10.5.1 Device Markings
    6. 10.6 Trademarks
    7. 10.7 Electrostatic Discharge Caution
    8. 10.8 Glossary
      1. 10.8.1 Video Timing Parameter Definitions
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

7.3.2 V-by-One Interface

The controller supports a single 8-lane V-by-One port, which can be configured for 1-, 2-, 4-, or 8-lane use. This interface supports limited lane remapping, which is shown in Table 7-2. Intralane remapping (that is, swapping P with N) is not supported.

Table 7-2 V-by-One Interface Lane Remapping Options
V-BY-ONE PORT PHYSICAL LANES(1)
CONFIGURATION(2)# of LANESLANE 7LANE 6LANE 5LANE 4LANE 3LANE 2LANE 1LANE 0
1a876543210
1b4————3210
1c2——————10
1d1———————0
2a810234567
2b41023————
2c210——————
2d1—0——————
(1) The lane numbers in the table header indicate the actual physical lanes defined in the controller interface. The lane numbers listed below the header are the lane bit numbers transmitted over that physical interface.
(2) There are two controller lane mapping options, with the option to use fewer than the full eight lanes for each.

Independent of the remapping of the physical V-by-One interface, the support a number of data mappings onto the actual physical interface as specified by the standard. V-by-One sources must match at least one of the mappings in Table 7-3, Table 7-4, Table 7-5, Table 7-6, Table 7-7, and Table 7-8.

Table 7-3 V-by-One Data Mapping for 36bpp/30bpp RGB/YCbCr 4:4:4
V-BY-ONE DATA MAP MODE 0
V-BY-ONE INPUT DATA BIT36bpp RGB/YCbCr 4:4:4(1)30bpp RGB/YCbCr 4:4:4MAPPER OUTPUT
D[0]R/Cr[4]R/Cr[2]B(2)
D[1]R/Cr[5]R/Cr[3]B(3)
D[2]R/Cr[6]R/Cr[4]B(4)
D[3]R/Cr[7]R/Cr(5]B(5)
D[4]R/Cr[8]R/Cr[6]B(6)
D[5]R/Cr[9]R/Cr[7]B(7)
D[6]R/Cr[10]R/Cr[8]B(8)
D[7]R/Cr[11]R/Cr[9]B(9)
D[8]G/Y[4]G/Y[2]A(2)
D[9]G/Y[5]G/Y[3]A(3)
D[10]G/Y[6]G/Y[4]A(4)
D[11]G/Y[7]G/Y[5]A(5)
D[12]G/Y[8]G/Y[6]A(6)
D[13]G/Y[9]G/Y[7]A(7)
D[14]G/Y[10]G/Y[8]A(8)
D[15]G/Y[11]G/Y[9]A(9)
D[16]B/Cb[4]B/Cb[2]C(2)
D[17]B/Cb[5]B/Cb[3]C(3)
D[18]B/Cb[6]B/Cb[4]C(4)
D[19]B/Cb[7]B/Cb[5]C(5)
D[20]B/Cb[8]B/Cb[6]C(6)
D[21]B/Cb[9]B/Cb[7]C(7)
D[22]B/Cb[10]B/Cb[8]C(8)
D[23]B/Cb[11]B/Cb[9]C(9)
D[24]3D_L/R_Ref3D_L/R_Ref3D_L/R_Ref
D[25]3DEN/Field3DEN/Field3DEN/Field
D[26]B/Cb[2]B/Cb[1]C[0]
D[27]B/Cb[3]B/Cb[0]C[1]
D[28]G/Y[2]G/Y[1]A[0]
D[29]G/Y[3]G/Y[0]A[1]
D[30]R/Cr[2]R/Cr[1]B[0]
D[31]R/Cr[3]R/Cr[0]B[1]
(1) For 36-bit inputs, the 12 bits per color truncates to 10 bits per color with the two least significant bits per color being discarded.
Table 7-4 V-by-One Data Mapping for 27bpp RGB/YCbCr 4:4:4
V-BY-ONE DATA MAP MODE 1
V-BY-ONE INPUT DATA BIT27bpp RGB/YCbCr 4:4:4(1)MAPPER OUTPUT
D[0]R/Cr[1]B(2)
D[1]R/Cr[2]B(3)
D[2]R/Cr[3]B(4)
D[3]R/Cr[4]B(5)
D[4]R/Cr[5]B(6)
D[5]R/Cr[6]B(7)
D[6]R/Cr[7]B(8)
D[7]R/Cr[8]B(9)
D[8]G/Y[1]A(2)
D[9]G/Y[2]A(3)
D[10]G/Y[3]A(4)
D[11]G/Y[4]A(5)
D[12]G/Y[5]A(6)
D[13]G/Y[6]A(7)
D[14]G/Y[7]A(8)
D[15]G/Y[8]A(9)
D[16]B/Cb[1]C(2)
D[17]B/Cb[2]C(3)
D[18]B/Cb[3]C(4)
D[19]B/Cb[4]C(5)
D[20]B/Cb[5]C(6)
D[21]B/Cb[6]C(7)
D[22]B/Cb[7]C(8)
D[23]B/Cb[8]C(9)
D[24]3D_L/R_Ref3D_L/R_Ref
D[25]3DEN/Field3DEN/Field
'0'—C[0]
D[27]B/Cb[0]C[1]
'0'—A[0]
D[29]G/Y[0]A[1]
'0'—B[0]
D[31]R/Cr[0]B[1]
(1) For 27-bit inputs, the 9 bits for each color shift up one bit, and the least significant bit of each color is set to '0'.
Table 7-5 V-by-One Data Mapping for 24bpp RGB/YCbCr 4:4:4
V-BY-ONE DATA MAP MODE 2
V-BY-ONE INPUT DATA BIT24bpp RGB/YCbCr 4:4:4(1)MAPPER OUTPUT
D[0]R/Cr[0]B(2)
D[1]R/Cr[1]B(3)
D[2]R/Cr[2]B(4)
D[3]R/Cr[3]B(5)
D[4]R/Cr[4]B(6)
D[5]R/Cr[5]B(7)
D[6]R/Cr[6]B(8)
D[7]R/Cr[7]B(9)
D[8]G/Y[0]A(2)
D[9]G/Y[1]A(3)
D[10]G/Y[2]A(4)
D[11]G/Y[3]A(5)
D[12]G/Y[4]A(6)
D[13]G/Y[5]A(7)
D[14]G/Y[6]A(8)
D[15]G/Y[7]A(9)
D[16]B/Cb[0]C(2)
D[17]B/Cb[1]C(3)
D[18]B/Cb[2]C(4)
D[19]B/Cb[3]C(5)
D[20]B/Cb[4]C(6)
D[21]B/Cb[5]C(7)
D[22]B/Cb[6]C(8)
D[23]B/Cb[7]C(9)
D[24]3D_L/R_Ref3D_L/R_Ref
D[25]3DEN/Field3DEN/Field
'0'—C[0]
'0'—C[1]
'0'—A[0]
'0'—A[1]
'0'—B[0]
'0'—B[1]
(1) For 24-bit inputs, the 8 bits for each color shift up two bits, and the two least significant bits of each color are set to '0'.
Table 7-6 V-by-One Data Mapping for 32bpp/24bpp/20bpp YCbCr 4:2:2
V-BY-ONE DATA MAP MODE 3(1)
V-BY-ONE INPUT DATA BIT32bpp YCbCr 4:2:2(2)24bpp YCbCr 4:2:2(3)20bpp YCbCr 4:2:2MAPPER OUTPUT
D[0]CbCr[8]CbCr[4]CbCr[2]B(2)
D[1]CbCr[9]CbCr[5]CbCr[3]B(3)
D[2]CbCr[10]CbCr[6]CbCr[4]B(4)
D[3]CbCr[11]CbCr[7]CbCr[5]B(5)
D[4]CbCr[12]CbCr[8]CbCr[6]B(6)
D[5]CbCr[13]CbCr[8]CbCr[7]B(7)
D[6]CbCr[14]CbCr[10]CbCr[8]B(8)
D[7]CbCr[15]CbCr[11]CbCr[9]B(9)
D[8]Y[8]Y[4]Y[2]A(2)
D[9]Y[9]Y[5]Y[3]A(3)
D[10]Y[10]Y[6]Y[4]A(4)
D[11]Y[11]Y[7]Y[5]A(5)
D[12]Y[12]Y[8]Y[6]A(6)
D[13]Y[13]Y[9]Y[7]A(7)
D[14]Y[14]Y[10]Y[8]A(8)
D[15]Y[15]Y[11]Y[9]A(9)
'0'———C(2)
'0'———C(3)
'0'———C(4)
'0'———C(5)
'0'———C(6)
'0'———C(7)
'0'———C(8)
'0'———C(9)
D[24]3D_L/R_Ref3D_L/R_Ref3D_L/R_Ref3D_L/R_Ref
D[25]3DEN/Field3DEN/Field3DEN/Field3DEN/Field
'0'———C[0]
'0'———C[1]
D[28]Y[6]Y[2]Y[2]A[0]
D[29]Y[7]Y[3]Y[3]A[1]
D[30]CbCr[6]CbCr[2]CbCr[2]B[0]
D[31]CbCr[7]CbCr[3]CbCr[3]B[1]
(1) For all YCbCr 4:2:2 formats, data channel C is forced to "0".
(2) For 32-bit inputs, the 16 bits per color truncate to 10-bit per color, with the six least significant bits per color discarded.
(3) For 24-bit inputs, the 12 bits per color truncate to 10-bit per color, with the two least significant bits per color discarded.
Table 7-7 V-by-One Data Mapping for 18bpp YCbCr 4:2:2
V-BY-ONE DATA MAP MODE 4(1)
V-BY-ONE INPUT DATA BIT18bpp YCbCr 4:2:2(2)MAPPER OUTPUT
D[0]CbCr[1]B(2)
D[1]CbCr[2]B(3)
D[2]CbCr[3]B(4)
D[3]CbCr[4]B(5)
D[4]CbCr[5]B(6)
D[5]CbCr[6]B(7)
D[6]CbCr[7]B(8)
D[7]CbCr[8]B(9)
D[8]Y[1]A(2)
D[9]Y[2]A(3)
D[10]Y[3]A(4)
D[11]Y[4]A(5)
D[12]Y[5]A(6)
D[13]Y[6]A(7)
D[14]Y[7]A(8)
D[15]Y[8]A(9)
'0'—C(2)
'0'—C(3)
'0'—C(4)
'0'—C(5)
'0'—C(6)
'0'—C(7)
'0'—C(8)
'0'—C(9)
D[24]3D_L/R_Ref3D_L/R_Ref
D[25]3DEN/Field3DEN/Field
'0'—C[0]
'0'—C[1]
'0'—A[0]
D[29]Y[0]A[1]
'0'—B[0]
D[31]CbCr[0]B[1]
(1) For all YCbCr 4:2:2 formats, data channel C is forced to "0".
(2) For 18-bit inputs, the 9 bits for each color shift up one bit, and the least significant bits of each color are set to '0'.
Table 7-8 V-by-One Data Mapping for 16bpp YCbCr 4:2:2
V-BY-ONE DATA MAP MODE 5(1)
V-BY-ONE INPUT DATA BIT16bpp YCbCr 4:2:2(2)MAPPER OUTPUT
D[0]CbCr[0]B(2)
D[1]CbCr[1]B(3)
D[2]CbCr[2]B(4)
D[3]CbCr[3]B(5)
D[4]CbCr[4]B(6)
D[5]CbCr[5]B(7)
D[6]CbCr[6]B(8)
D[7]CbCr[7]B(9)
D[8]Y[0]A(2)
D[9]Y[1]A(3)
D[10]Y[2]A(4)
D[11]Y[3]A(5)
D[12]Y[4]A(6)
D[13]Y[5]A(7)
D[14]Y[6]A(8)
D[15]Y[7]A(9)
'0'—C(2)
'0'—C(3)
'0'—C(4)
'0'—C(5)
'0'—C(6)
'0'—C(7)
'0'—C(8)
'0'—C(9)
D[24]3D_L/R_Ref3D_L/R_Ref
D[25]3DEN/Field3DEN/Field
'0'—C[0]
'0'—C[1]
'0'—A[0]
'0'—A[1]
'0'—B[0]
'0'—B[1]
(1) For all YCbCr 4:2:2 formats, data channel C is forced to "0".
(2) For 16-bit inputs, the 8 bits for each color shift up one bit, and the least significant bit of each color is set to '0'.