DLPS292 July   2025 DLPC8424 , DLPC8444 , DLPC8454

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Compatability Table
  6. 5 Pin Configuration and Functions
    1.     7
    2. 5.1  Initialization, Board Level Test, and Debug
    3. 5.2  V-by-One Interface Input Data and Control
    4. 5.3  FPD-Link Port(s) Input Data and Control
    5. 5.4  DSI Input Data and Clock (Not Supported in DLPC8424, DLPC8444, and DLPC8454)
    6. 5.5  DMD SubLVDS Interface
    7. 5.6  DMD Reset and Low-Speed Interfaces
    8. 5.7  Flash Interface
    9. 5.8  Peripheral Interfaces
    10. 5.9  GPIO Peripheral Interface
    11. 5.10 Clock and PLL Support
    12. 5.11 Power and Ground
    13. 5.12 I/O Type Subscript Definition
    14. 5.13 Internal Pullup and Pulldown Characteristics
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2.     23
    3. 6.2  ESD Ratings
    4. 6.3  Recommended Operating Conditions
    5. 6.4  Thermal Information
    6. 6.5  Power Electrical Characteristics
    7. 6.6  Pin Electrical Characteristics
    8. 6.7  DMD SubLVDS Interface Electrical Characteristics
    9.     30
    10. 6.8  DMD Low-Speed Interface Electrical Characteristics
    11.     32
    12. 6.9  V-by-One Interface Electrical Characteristics
    13. 6.10 FPD Link LVDS Electrical Characteristics
    14. 6.11 USB Electrical Characteristics
    15.     36
    16. 6.12 System Oscillator Timing Requirements
    17.     38
    18. 6.13 Power Supply and Reset Timing Requirements
    19.     40
    20. 6.14 V-by-One Interface General Timing Requirements
    21.     42
    22. 6.15 FPD Link Interface General Timing Requirements
    23. 6.16 Flash Interface Timing Requirements
    24.     45
    25. 6.17 Source Frame Timing Requirements
    26.     47
    27. 6.18 Synchronous Serial Port Interface Timing Requirements
    28.     49
    29. 6.19 I2C Interface Timing Requirements
    30. 6.20 Programmable Output Clock Timing Requirements
    31. 6.21 JTAG Boundary Scan Interface Timing Requirements (Debug Only)
    32.     53
    33. 6.22 DMD Low-Speed Interface Timing Requirements
    34.     55
    35. 6.23 DMD SubLVDS Interface Timing Requirements
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagrams
    3. 7.3 Feature Description
      1. 7.3.1 Input Sources
      2. 7.3.2 V-by-One Interface
      3. 7.3.3 FPD-Link Interface
      4. 7.3.4 DMD (SubLVDS) Interface
      5. 7.3.5 Serial Flash Interface
      6. 7.3.6 GPIO Supported Functionality
        1.       67
        2.       68
      7. 7.3.7 Debug Support
  9. 8 Power Supply Recommendations
    1. 8.1 System Power-Up and Power-Down Sequence
    2. 8.2 DMD Fast Park Control (PARKZ)
    3. 8.3 Power Supply Management
    4. 8.4 Hotplug Usage
    5. 8.5 Power Supplies for Unused Input Source Interfaces
    6. 8.6 Power Supplies
      1. 8.6.1 Power Supplies DLPA3085 or DLPA3082
  10. 9 Layout
    1. 9.1 Layout Guidelines
      1. 9.1.1 Layout Guideline for DLPC8424 or DLPC8444 or DLPC8454 Reference Clock
        1. 9.1.1.1 Recommended Crystal Oscillator Configuration
      2. 9.1.2 V-by-One Interface Layout Considerations
      3. 9.1.3 DMD Maximum Pin-to-Pin, PCB Interconnects Etch Lengths
      4. 9.1.4 Power Supply Layout Guidelines
    2. 9.2 Thermal Considerations
  11. 10Device and Documentation Support
    1. 10.1 Third-Party Products Disclaimer
    2. 10.2 Documentation Support
      1. 10.2.1 Related Documentation
    3. 10.3 Receiving Notification of Documentation Updates
    4. 10.4 Support Resources
    5. 10.5 Device Nomenclature
      1. 10.5.1 Device Markings
    6. 10.6 Trademarks
    7. 10.7 Electrostatic Discharge Caution
    8. 10.8 Glossary
      1. 10.8.1 Video Timing Parameter Definitions
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

8.1 System Power-Up and Power-Down Sequence

Although the controller requires an array of power supply voltage pins, there are no restrictions regarding the relative order of power supply sequencing to avoid damaging the controller (this remains true for both power-up and power-down scenarios). The controllers require no minimum delay time between powering up and powering down the individual supplies. Additional power sequencing rules may exist for devices that share supplies with the controller (such as the PMIC and DMD). These devices may force additional system power sequencing requirements. The controller power-up sequence, the normal PARK power-down sequence, and the fast PARK power-down sequence of a typical DLPC system are shown in the following figures.

DLPC8424 DLPC8444 DLPC8454 System Power-Up Waveforms (with DLPA3085 or DLPA3082)

t1:Power applied to the system. All other voltage rails are derived from system input power.
t2:All supplies reach 95% of their specified nominal value. Note HOST_IRQ is an open-drain output.
t3:Point where RESETZ is deasserted (goes high). This marks the beginning of auto-initialization.
t4:HOST_IRQ goes high to indicate initialization is complete and host communication may begin.
(a):PARKZ and PROJ_ON should be high prior to RESETZ release to support auto-initialization.
(b):tRAMP-UP-TOTAL, maximum time from 0.8V ramp start to all supplies stable.
(c):tREFCLK, the minimum time reference clock must be stable before releasing RESETZ.
(d):I2C activity cannot start until HOST_IRQ goes high to indicate auto-initialization is completed.

Figure 8-1 System Power-Up Waveforms (with DLPA3085 or DLPA3082)
DLPC8424 DLPC8444 DLPC8454 Normal Park Power-Down Waveforms

t1:PROJ_ON goes low to begin the power-down sequence.
t2:The controller completes the DMD mirror parking sequence.
t3:RESETZ is asserted, HOST_IRQ goes high.
t4:All controller power supplies are turned off and discharged.
t5:System power can safely be removed.
(a):I2C activity after PROJ_ON is deasserted (goes low) is not supported.
(b):DMD mirror parking sequence begins when PROJ_ON is deasserted (going low).
(c):It is recommended that system input power be maintained within specifications well after PROJ_ON is deasserted (goes low) to allow time for DMD parking and supplies to fully power down.
(d):DLPA PMIC controls the controller's supply power-down timing.

Figure 8-2 Normal Park Power-Down Waveforms
DLPC8424 DLPC8444 DLPC8454 Fast Park Power-Down Waveforms

t1:A fault is detected (in this example, the PMIC detects a UVLO condition) and PARKZ is asserted (goes low) to tell the controller to initiate a fast park of the DMD.
t2:The controller finishes the fast park procedure.
t3:RESETZ is asserted, which puts the controller in a reset state that releases HOST_IRQ to a high.
t4:Eventually, all power supplies that were derived from SYSPWR collapse.
(a):All power supplies and the PLL_REFCLK must be held within specification for a minimum of 32μs after PARKZ is asserted (goes low) to protect DMD from possible damage.
(b):The DMD has power sequencing requirements that may impact the timing requirements of a 1.8V supply, refer to the DMD data sheet for more information.

Figure 8-3 Fast Park Power-Down Waveforms