The unipolar excitation voltage, V_EXCITATION, is used as the ADC supply voltage (AVDD) as well as the ADC reference voltage, V_REF. Small variations in the bridge resistance due to tension or compression cause the differential output voltage for each bridge to change. The bridge output voltage is reduced compared to a single bridge measurement because V_EXCITATION is divided between Bridge A and Bridge B. The PGA integrated into the ADC gains up the low-level bridge output signal to reduce system noise and utilize more of the ADC full-scale range (FSR). The ADC samples and converts this amplified voltage against V_REF. This measurement is not ratiometric because the output voltage of Bridge A can change depending on the properties of Bridge B (and vice versa). This dependence occurs even in the absence of a change in the applied load, resulting in a pseudo-ratiometric reference configuration. This challenge can be removed by using a dedicated set of reference inputs per bridge, assuming the ADC has multiple differential reference inputs.

Measuring multiple four-wire resistive bridges in series using a pseudo-ratiometric reference and a unipolar, low-voltage (≤ 5 V) supply requires:

• Multiple differential analog inputs (AINPx and AINNx) or external multiplexer
• External reference input (dedicated pin or use analog supply)
• Low-noise amplifier

When implementing a circuit with multiple bridges in series, it is important to use sensors with similar parameters (should be the same for each bridge) as mentioned in Table 6-18. Following this guideline simplifies how the common-mode voltage for each bridge is determined. Additionally, using bridges with different nominal resistances can introduce gain errors as well as make it more challenging to determine the load weight. This latter challenge can be removed by using a dedicated set of reference inputs per bridge, assuming the ADC has multiple differential reference inputs.

To begin a design, start by using the equations in Table 6-19 to calculate the bridge output common-mode voltage, V_{CM(Bridge_A)} and V_{CM(Bridge_B)}, under a no-load condition (R1 = R2 = R3 = R4). For example, if R_BRIDGE = 1 kΩ and V_EXCITATION = 5 V, Equation 65 and Equation 66 yield the following results:

Figure 6-12 shows the voltage level at each input of the ADC multiplexer and how each will be applied to the same amplifier.

Figure 6-12 Common-Mode Voltage for Two Bridges in a Series Configuration

Unlike the previous examples where one of the system parameters was a specific ADC amplifier common-mode voltage target, a series combination of bridges requires identifying the ADC amplifier common-mode voltage range, V_{CM(ADC)_RANGE}. This range helps accommodate a potentially wide variance between V_{CM(Bridge_A)} and V_{CM(Bridge_B)}, which is the case in Figure 6-12. As described in Section 6.3.4, many ADCs used for bridge measurement applications have support collateral that can help identify the ADC amplifier common-mode range for a particular set of input conditions.

Figure 6-13 shows an example of how the Common-Mode Range Calculator from the ADS1261 Excel Calculator can be used to determine if V_{CM(Bridge_A)} and V_{CM(Bridge_B)} are within the input range of the amplifier integrated into the ADS1261.

Figure 6-13 Verifying System Requirements Using the ADS1261 VCM Calculator Tool

In Figure 6-13, VIN_CM = 3.75 V to check if the ADC amplifier can accept V_{CM(Bridge_A)}. The tool shows no errors for an input signal with this common-mode voltage, indicating that this is a valid input condition when gain = 128, AVDD = 5 V, and VIN_DIFF = 10 mV (though not shown, VIN_CM = 1.25 V is also a valid input condition). Moreover, the tool shows that for these specific settings, V_{CM(ADC)_RANGE} extends from 0.45 V to 4.54 V, indicating that the ADC amplifier can accept both V_{CM(Bridge_A)} and V_{CM(Bridge_B)}.

Note that V_{CM(ADC)_RANGE} depends on the PGA gain in this example. Therefore, the PGA gain for each bridge must be selected in conjunction with confirming that V_{CM(Bridge_A)} and V_{CM(Bridge_B)} are within V_{CM(ADC)_RANGE}. The PGA gain should be the largest allowable value that is still less than the ADC FSR. In some cases it is not possible to choose an amplifier gain that uses the entire ADC FSR. While this is often an acceptable tradeoff between resolution and ease-of-use, care should be taken to ensure that all system requirements are still met when the ADC FSR cannot be maximized.

Next, identify the maximum differential output voltage of each bridge, V_{OUT(Bridge Max)}, using the equation from Table 6-19 and parameters from Table 6-18. This value provides the maximum output voltage possible from the bridge under normal operating conditions and corresponds to the maximum load that can be applied to the bridge, Load_{(Bridge Max)}. If the system does not use the entire bridge output range, V_{OUT(System Max)} defines the maximum differential output signal that is applied to a specific system and Load_{(System Max)} is the corresponding maximum load. For example, if V_{OUT(Bridge Max)} corresponds to Load_{(Bridge Max)} = 5 kg, but the system specifications only require that Load(System Max) = 2.5 kg, then V_{OUT(System Max)} is given by Equation 67:

Note that if Load_{(System Max)} = Load_{(Bridge Max)}, then V_{OUT(System Max)} = V_{OUT(Bridge Max)}.

Finally, follow the instructions in Section 5.5 if calibration is required. Note that each bridge in Figure 6-11 must be calibrated separately, requiring the host processor to calculate and store multiple sets of calibration coefficients.