The unipolar excitation voltage, V_EXCITATION, is used as the ADC supply voltage (AVDD) as well as the ADC reference voltage, V_REF. Small variations in the bridge resistance due to tension or compression change the differential output voltage for each bridge. The circuit configuration combines and averages the output of each bridge to generate a voltage that is proportional to the applied load. The PGA integrated into the ADC gains up this low-level signal to reduce system noise and utilize more of the ADC full-scale range (FSR). The ADC samples and converts this amplified voltage against V_REF, which is the same voltage used to excite each bridge and therefore ratiometric. The excitation source noise and drift are seen equally in both V_IN and V_REF in a ratiometric reference configuration, effectively removing these errors from the ADC output code.

Measuring multiple four-wire resistive bridges in parallel using a single-channel ADC, a ratiometric reference, and a unipolar, low-voltage (≤ 5 V) supply requires:

• Differential analog inputs (AINP and AINN)
• External reference input (dedicated pin or use analog supply)
• Low-noise amplifier

When measuring multiple bridges in parallel using a multichannel ADC, the ADC measures each bridge individually and the host processor sums these values together to determine the applied load. When measuring multiple bridges in parallel using a single-channel ADC, this summation occurs before the input signal is applied to the ADC. To understand how the bridge circuit in Figure 6-14 yields a voltage proportional to the applied load, it is helpful to convert each bridge into its Thevenin equivalent.

Figure 6-15 derives the Thevenin equivalent of the standard bridge circuit using the assumption that R >> ΔR.

Figure 6-15 Thevenin Equivalent of a Single Bridge Circuit

In Figure 6-15, V_TH+ and V_TH– can be calculated using Equation 71 and Equation 72, respectively:

Figure 6-16 applies the result from Figure 6-15 to show the Thevenin equivalent circuit for all four bridges in Figure 6-14 (Bridge A, B, C, and D). This result helps determine how the complete bridge circuit yields an output voltage proportional to the applied load.

Figure 6-16 Thevenin Equivalent of Four Bridge Circuits in Parallel

Equation 73 defines the differential bridge output voltage at V_SIGNAL± that is applied to the ADC inputs, V_IN, in Figure 6-14:

Assuming RA = RB = RC = RD = R such that all nominal bridge resistances are identical, Equation 73 reduces to Equation 74:

Ultimately, V_IN is proportional to V_EXCITATION scaled by the average value of the change in each bridge resistance.

To understand how the result in Equation 74 translates to a real system, one common application for measuring multiple resistive bridges in parallel using a single-channel ADC is determining the weight of a load on a platform. The bridges are placed at specific points around the platform, and the weight of the load is determined by the methodology described in this section. This is especially useful when the load is not centered on the platform because the weight measured by each bridge scales relative to the distance from the load. A red, centered load is shown in Figure 6-17 (left) while a non-centered load is shown in Figure 6-17 (right). Each platform in Figure 6-17 has four bridges (in blue), similar to the circuit shown in Figure 6-14.

Figure 6-17 Measuring a Load on a Platform Using Multiple Bridges in Parallel: Centered Load (left) and Non-Centered Load (right)

In Figure 6-17 (left), each bridge ideally measures 1/4 of the overall load when the load is centered on the platform. When the load is not centered, as shown in Figure 6-17 (right), Bridge 1 (B1) and Bridge 3 (B3) measure a larger percentage of the overall load compared to Bridge 2 (B2) and Bridge 4 (B4). For example, B1 and B3 might each measure 45% of the total load, while B2 and B4 only measure 5% each. As a result, it is important to use bridges with similar parameters (Should be the same for each bridge) as mentioned in Table 6-18. Using the same component for each bridge in a parallel configuration with a single-channel ADC helps simplify the calculations that determine the total load.

Specifically, the total load, Load_{(System Max)}, in this parallel bridge configuration is equal to the sum of the maximum load that can be applied to each bridge, Load_{(Bridge Max)}. Assuming the table note for Table 6-18 is respected such that Load_{(Bridge Max)} is the same for all bridges, then Load_{(System Max)} = # of bridges • Load_{(Bridge Max)}. For example, if Load_{(Bridge Max)} = 5 kg for each bridge in Figure 6-14, then Load_{(System Max)} = 4 • 5 kg = 20 kg. Therefore, it is possible that each bridge can deliver the maximum differential output voltage, V_{OUT(Bridge Max)}, at any time. Since this specific circuit configuration combines the output voltage of each bridge to create V_SIGNAL±, it is also necessary to determine the maximum signal that can be applied to the ADC, V_OUT(Max), as per Table 6-19.

After V_OUT(Max) has been determined, choose the corresponding gain value for the ADC PGA. The amplifier gain should be the largest allowable value that is still less than the ADC FSR. In some cases it is not possible to choose an amplifier gain that uses the entire ADC FSR. While this is often an acceptable tradeoff between resolution and ease-of-use, care should be taken to ensure that all system requirements are still met when the ADC FSR cannot be maximized.

Next, ensure that the bridge output common-mode voltage, V_CM(Bridge), defined in Table 6-19 is within the common-mode range of the ADC amplifier, V_CM(ADC), under a no-load condition (R1 = R2 = R3 = R4). The amplifier common-mode range varies by component, and is defined in the data sheet based on the gain setting and supply voltage. However, targeting V_CM(Bridge) = AVDD / 2 is a good choice as this is typically in the center of the V_CM(ADC) range, enabling the highest gain possible per the previous step. Moreover, the bridge configuration in Figure 6-14 inherently sets V_CM(Bridge) to AVDD / 2 under a no-load condition when V_EXCITATION = AVDD.

Finally, the circuit in Figure 6-14 introduces an additional challenge in that there is no easy way to calibrate each bridge because they all share the V_SIGNAL± leads. This is dissimilar from a circuit with multiple bridges in parallel using a multichannel ADC because each bridge is measured independently in that case. That circuit configuration allows the host processor to derive specific calibration coefficients for each bridge and remove the measurement error before summation. Comparatively, the system in Figure 6-14 combines all of the bridge errors together. This results in a single set of calibration coefficients that are only applicable to the specific settings used during the calibration procedure.

To demonstrate why this issue occurs, Figure 6-18 plots hypothetical bridge responses for a weight-measurement system similar to Figure 6-17. In this example, V_REF = V_EXCITATION = 5 V, while each bridge has a sensitivity of 2 mV/V and Load_{(Bridge Max)} = 2 kg. This system also has an applied load, W, of 2 kg.

Figure 6-18 Calibrating a Weigh Scale System Using Four Bridges in Parallel With a Single-Channel ADC

Each of the four bridges in this example would have V_{OUT(Bridge Max)} = V_{OUT(Ideal Max)} = 10 mV if they all followed the green, ideal response in Figure 6-18. However, this example assumes each sensor has some offset value. As shown in the blue plots in Figure 6-18, B1 has an offset of 1 mV (B_{Actual_B1} = 1 mV), B_{Actual_B2} = 2 mV, B_{Actual_B3} = 3 mV, and B_{Actual_B4} = 4 mV. The offset-affected bridge response changes V_{OUT(Bridge Max)} for each bridge (V_{OUT(Bx Max)}). The output voltage, V_B, for a single bridge in this example is given by Equation 75:

In Equation 75, the scaling factor P_Bridge is the percentage of the total load measured by that specific bridge. Assuming a centered load as per Figure 6-17 (left), all four bridges in Figure 6-18 have P_Bridge = 1/4 = 25%. This is true whether they are ideal (green plot) or offset-affected (blue plots).

When P_Bridge = 25%, W = 2 kg, and Load_{(Bridge Max)} = 2 kg, each of the four bridges represented by the green, ideal plot have an output voltage of 2.5 mV. This results in a total output voltage at V_SIGNAL± of 4 ∙ 2.5 mV = 10 mV. Comparatively, applying Equation 75 to the four blue, offset-affected bridge responses in Figure 6-18 yields the results in Equation 76 through Equation 79:

The total output voltage applied to V_SIGNAL± is the sum of the results in Equation 76 through Equation 79, or
12.5 mV. This value includes an error of 2.5 mV compared to the ideal voltage of 10 mV. This error voltage is stored in the host processor as the offset calibration coefficient and removed from each subsequent measurement.

Next, assume the load is moved between B1 and B3 as shown in Figure 6-17 (right). In this case, the portion of the load measured by each bridge is unequal, which changes the output voltage from each bridge. Using the same distribution given earlier in this section (P_B1 = P_B3 = 45 %, P_B2 = P_B4 = 5%), the resulting output voltage from each bridge is given by Equation 80 through Equation 83:

Similar to the centered-load case, the total output voltage applied to V_SIGNAL± is the sum of all V_Bx, or 12.1 mV. Subtracting the previously determined offset error value of 2.5 mV gives a calibrated voltage of 9.6 mV, resulting in a 4% error compared to the ideal value (10 mV). This outcome occurs despite the fact that the only difference between the first and second scenario is the location of the load on the scale. Accounting for other common errors such as sensitivity tolerance, ADC errors, gain error from the lead resistance, and variation in the nominal bridge resistances could further reduce the system accuracy.

Ultimately, systems that measure multiple bridges in parallel using a single-channel ADC require well-matched bridge sensors with similar specifications to maintain high performance results. Another option is to use an external summing box that calibrates any differences among the bridge sensors before the summation occurs. Finally, some low-accuracy systems may find the level of performance of this circuit acceptable compared to the increased throughput and ease-of-design.