SBASAI9 December   2025 ADS122S14

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Switching Characteristics
    8. 5.8 Timing Diagrams
    9. 5.9 Typical Characteristics
  7. 6 Parameter Measurement Information
    1. 6.1 Noise Performance
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Analog Inputs and Multiplexer
      2. 7.3.2  Programmable Gain Amplifier (PGA)
      3. 7.3.3  Voltage Reference
        1. 7.3.3.1 Internal Reference
        2. 7.3.3.2 External Reference
        3. 7.3.3.3 Reference Buffers
      4. 7.3.4  Clock Source
      5. 7.3.5  Delta-Sigma Modulator
      6. 7.3.6  Digital Filter
        1. 7.3.6.1 Sinc4 and Sinc4 + Sinc1 Filter
        2. 7.3.6.2 FIR Filter
        3. 7.3.6.3 Digital Filter Latency
        4. 7.3.6.4 Global-Chop Mode
      7. 7.3.7  Excitation Current Sources (IDACs)
      8. 7.3.8  Burn-Out Current Sources (BOCS)
      9. 7.3.9  General Purpose IOs (GPIOs)
        1. 7.3.9.1 FAULT Output
        2. 7.3.9.2 DRDY Output
      10. 7.3.10 System Monitors
        1. 7.3.10.1 Internal Short (Offset Calibration)
        2. 7.3.10.2 Internal Temperature Sensor
        3. 7.3.10.3 External Reference Voltage Readback
        4. 7.3.10.4 Power-Supply Readback
      11. 7.3.11 Monitors and Status Flags
        1. 7.3.11.1 Reset (RESETn flag)
        2. 7.3.11.2 AVDD Undervoltage Monitor (AVDD_UVn flag)
        3. 7.3.11.3 Reference Undervoltage Monitor (REV_UVn flag)
        4. 7.3.11.4 SPI CRC Fault (SPI_CRC_FAULTn flag)
        5. 7.3.11.5 Register Map CRC Fault (REG_MAP_CRC_FAULTn flag)
        6. 7.3.11.6 Internal Memory Fault (MEM_FAULTn flag)
        7. 7.3.11.7 Register Write Fault (REG_WRITE_FAULTn flag)
        8. 7.3.11.8 DRDY Indicator (DRDY bit)
        9. 7.3.11.9 Conversion Counter (CONV_COUNT[3:0])
    4. 7.4 Device Functional Modes
      1. 7.4.1 Power-up and Reset
        1. 7.4.1.1 Power-On Reset (POR)
        2. 7.4.1.2 Reset by Register Write
        3. 7.4.1.3 Reset by SPI Input Pattern
      2. 7.4.2 Operating Modes
        1. 7.4.2.1 Idle and Standby Mode
        2. 7.4.2.2 Power-Down Mode
        3. 7.4.2.3 Power-Scalable Conversion Modes
          1. 7.4.2.3.1 Continuous-Conversion Mode
          2. 7.4.2.3.2 Single-shot Conversion Mode
    5. 7.5 Programming
      1. 7.5.1  Serial Interface (SPI)
      2. 7.5.2  Serial Interface Signals
        1. 7.5.2.1 Chip Select (CS)
        2. 7.5.2.2 Serial Clock (SCLK)
        3. 7.5.2.3 Serial Data Input (SDI)
        4. 7.5.2.4 Serial Data Output/Data Ready (SDO/DRDY)
        5. 7.5.2.5 Data Ready (DRDY) Pin
      3. 7.5.3  Serial Interface Communication Structure
        1. 7.5.3.1 SPI Frame
        2. 7.5.3.2 STATUS Header
        3. 7.5.3.3 SPI CRC
      4. 7.5.4  Device Commands
        1. 7.5.4.1 No Operation (Read Conversion Data)
        2. 7.5.4.2 Read Register Command
        3. 7.5.4.3 Write Register Command
      5. 7.5.5  Continuous-Read Mode
        1. 7.5.5.1 Read Registers in Continuous-Read Mode
      6. 7.5.6  Daisy-Chain Operation
      7. 7.5.7  3-Wire SPI Mode
        1. 7.5.7.1 3-Wire SPI Mode Frame Re-Alignment
      8. 7.5.8  Monitoring for New Conversion Data
        1. 7.5.8.1 DRDY Pin or SDO/DRDY Pin Monitoring
        2. 7.5.8.2 Reading DRDY Bit and Conversion Counter
        3. 7.5.8.3 Clock Counting
      9. 7.5.9  DRDY Pin Behavior
      10. 7.5.10 Conversion Data Format
      11. 7.5.11 Register Map CRC
  9. 8 Registers
  10. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Serial Interface Connections
      2. 9.1.2 Interfacing with Multiple Devices
      3. 9.1.3 Unused Inputs and Outputs
      4. 9.1.4 Device Initialization
    2. 9.2 Typical Applications
      1. 9.2.1 Software-Configurable RTD Measurement Input
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Performance Plots
        4. 9.2.1.4 Design Variant – 3-Wire RTD Measurement With Automatic Lead-Wire Compensation Using Two IDACs
      2. 9.2.2 Thermocouple Measurement With Cold-Junction Compensation Using a 2-wire RTD
      3. 9.2.3 Resistive Bridge Sensor Measurement With Temperature Compensation
    3. 9.3 Power Supply Recommendations
      1. 9.3.1 Power Supplies
      2. 9.3.2 Power-Supply Sequencing
      3. 9.3.3 Power-Supply Decoupling
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

5.5 Electrical Characteristics

minimum and maximum specifications apply from TA = –40°C to +125°C; typical specifications are at TA = 25°C; all specifications are at AVDD = 1.74V to 3.6V, DVDD = 1.65V to 3.6V, internal reference, internal oscillator, all speed modes, all data rates, all gain settings, and global chop disabled (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
ANALOG INPUTS
Absolute input current(1) All gains, fDATA = 20SPS or 25SPS,
global chop enabled or disabled,
VAINx(MIN) ≤ VAINx ≤ VAINx(MAX), VIN = 0V		 –2 ±0.3 2 nA
Absolute input current drift(1) All gains, fDATA = 20SPS or 25SPS,
global chop enabled or disabled,
VAINx(MIN) ≤ VAINx ≤ VAINx(MAX), VIN = 0V		 2 pA/°C
Differential input current(1) All gains, fDATA = 20SPS or 25SPS,
global chop enabled or disabled,
VCM = AVDD/2, –VREF/Gain ≤ VIN ≤ VREF/Gain		 –2 ±0.1 2 nA
Differential input current drift(1) All gains, fDATA = 20SPS or 25SPS,
global chop enabled or disabled,
VCM = AVDD/2, –VREF/Gain ≤ VIN ≤ VREF/Gain		 2 pA/°C
PGA
Gain settings 0.5, 1, 2, 4, 5, 8, 10, 16, 20, 32, 50, 64, 100, 128, 200, 256
SYSTEM PERFORMANCE
Resolution (no missing codes) ADS112S14 16 Bits
ADS122S14 24
fDATA Output data rate Speed mode 0 (fMOD = 32kHz) 20 2k SPS
Speed mode 1 (fMOD = 256kHz) 20 16k
Speed mode 2 (fMOD = 512kHz) 20 32k
Speed mode 3 (fMOD = 1024kHz) 20 64k
INL Integral nonlinearity VCM = AVDD/2, best fit 5 15 ppmFSR
VIO Input offset voltage TA = 25°C, gain = 0.5, global chop disabled –250 ±50 250 µV
TA = 25°C, gains = 1 to 10, global chop disabled –150 ±20 150
TA = 25°C, gain ≥ 16, global chop disabled –50 ±10 50
TA = 25°C, gain = 0.5, global chop enabled –5 ±0.5 5
TA = 25°C, gain ≥ 1, global chop enabled –2 ±0.2 2
Offset drift Gains ≤ 10, global chop disabled 60 300 nV/°C
Gains ≥ 16, global chop disabled 20 125
All gains, global chop enabled 10 50
Gain error TA = 25°C, all gains, external reference –0.3 ±0.08 0.3 %
Gain drift All gains, external reference 0.5 2.5 ppm/°C
Noise (input-referred) See the Noise Performance section
NMRR Normal-mode rejection ratio fIN = 50Hz or 60Hz (±1Hz), fDATA = 20SPS 82 95 dB
fIN = 50Hz or 60Hz (±1Hz), fDATA = 20SPS, external fCLK = 4.096MHz 95
fIN = 50Hz or 60Hz (±1Hz), fDATA = 25SPS 57 62
fIN = 50Hz or 60Hz (±1Hz), fDATA = 25SPS, external fCLK = 4.096MHz 62
CMRR Common-mode rejection ratio At dc 120 dB
fCM = 50Hz or 60Hz (±1Hz), fDATA = 20SPS or 25SPS 130
fCM = 50Hz or 60Hz (±1Hz), fDATA > 25SPS 120
PSRR Power-supply rejection ratio AVDD at dc 110 dB
DVDD at dc 115
VOLTAGE REFERENCE INPUTS
Absolute input current REF buffer disabled, speed mode 0(2) –1.5 ±1 1.5 µA/V
REF buffer disabled, speed mode 1(2) –7 ±6 7
REF buffer disabled, speed mode 2(2) –8 ±7 8
REF buffer disabled, speed mode 3(2) –9 ±8 9
REF buffer enabled, speed mode 0 –2 ±0.2 2 nA
REF buffer enabled, speed mode 1 3 7
REF buffer enabled, speed mode 2 10 12
REF buffer enabled, speed mode 3 17 23
INTERNAL VOLTAGE REFERENCE
VREF Output voltage AVDD < 2.7V 1.25 V
AVDD ≥ 2.7V 1.25, 2.5
Accuracy TA = 25°C –0.15 ±0.05 0.15 %
Temperature drift 10 25 ppm/°C
Output current VREF = 1.25V, sink or source –5 5 mA
VREF = 2.5V, AVDD ≥ 2.75V, sink or source –10 5
Short-circuit current limit Sink or source ±25 mA
PSRR Power-supply rejection ratio AVDD at dc 90 dB
Load regulation Load current = –5mA to 0mA (source) 100 µV/mA
Capacitive load stability 50 100 1300 nF
Reference noise f = 0.1Hz to 10Hz, 100nF capacitor on REFOUT 4 ppmPP
Start-up time From power-down mode, 100nF capacitor on REFOUT, 0.01% settling 10 ms
INTERNAL OSCILLATOR
fOSC Frequency 4.096 MHz
Accuracy –1 1 %
EXCITATION CURRENT SOURCES (IDACS)
Current settings IDAC unit current = 1µA 1 to 100 µA
IDAC unit current = 10µA, AVDD < 2.7V 10 to 500
IDAC unit current = 10µA, AVDD ≥ 2.7V 10 to 1000
Compliance voltage IIDAC <100µA, current changes by less than 1% from (AVDD – 1V) GND AVDD – 0.3 V
IIDAC = 100µA to 700µA, current changes by less than 1% from (AVDD – 1V) GND AVDD – 0.4
IIDAC current ≥ 800µA, current changes by less than 1% from (AVDD – 1V) GND AVDD – 0.45
Accuracy IIDAC = 1µA, TA = 25°C –6 ±0.4 6 %
IIDAC = 10µA to 1mA, TA = 25°C –3 ±0.4 3
Current mismatch between IDACs IIDAC ≤ 10µA, IDAC1 and IDAC2 set to same value,
TA = 25°C		 0.5 2 %
IIDAC ≥ 20µA, IDAC1 and IDAC2 set to same value,
TA = 25°C		 0.05 0.5
Temperature drift IIDAC = 1µA 50 300 ppm/°C
IIDAC ≥ 10µA 25 110
Temperature drift matching IIDAC ≤ 10µA, IDAC1 and IDAC2 set to same value 12 70 ppm/°C
IIDAC ≥ 20µA, IDAC1 and IDAC2 set to same value 1 10
BURNOUT CURRENT SOURCES (BOCS)
Current settings 0.2, 1, 10 µA
Accuracy Sink and source ±2 %
TEMPERATURE SENSOR
TSOffset Output voltage TA = 25°C 119.5 mV
TSTC Temperature coefficient 405 µV/°C
MONITORS
THDVDD_POR DVDD POR threshold 1.55 V
THAVDD_UV AVDD undervoltage threshold(3) 1.2 1.5 V
THREF_UV Reference undervoltage threshold(3) 0.5 0.6 V
System monitor voltage readback accuracy (VREFP – VREFN) / 8 ±0.5 %
AVDD / 8 ±1
DVDD / 8 ±1
GENERAL-PURPOSE INPUTS/OUTPUTS (GPIOs)
VIL Logic input level, low GND 0.3 AVDD V
VIH Logic input level, high 0.7 AVDD AVDD V
VOL Logic output level, low IOL = 100µA, open-drain or push-pull output GND 0.2 AVDD V
VOH Logic output level, high IOH = –100µA, push-pull output 0.8 AVDD AVDD V
Input hysteresis 10 mV
DIGITAL INPUTS/OUTPUTS
VIL Logic input level, low GND 0.3 DVDD V
VIH Logic input level, high 0.7 DVDD DVDD V
VOL Logic output level, low IOL = 1mA GND 0.2 DVDD V
VOH Logic output level, high IOH = –1mA 0.8 DVDD DVDD V
Input hysteresis 180 mV
Input current GND ≤ VDigital Input ≤ DVDD –1 1 µA
ANALOG SUPPLY CURRENTS (AVDD = 3.3V, External Reference, Reference Buffers Disabled, IDACs Disabled, All Data Rates, VIN = 0V)
IAVDD Analog supply current Power-down mode 0.2 2 µA
Standby mode 10 16
Conversion mode, speed mode 0, gain = 0.5 to 2 52 59
Conversion mode, speed mode 0, gain = 4 and 5 55 63
Conversion mode, speed mode 0, gain = 8 to 50 61 68
Conversion mode, speed mode 0, gain = 64 to 256 57 64
Conversion mode, speed mode 1, gain = 0.5 to 2 135 145
Conversion mode, speed mode 1, gain = 4 and 5 155 170
Conversion mode, speed mode 1, gain = 8 to 50 205 220
Conversion mode, speed mode 1, gain = 64 to 256 255 275
Conversion mode, speed mode 2, gain = 0.5 to 2 315 335
Conversion mode, speed mode 2, gain = 4 and 5 360 380
Conversion mode, speed mode 2, gain = 8 to 50 450 480
Conversion mode, speed mode 2, gain = 64 to 256 670 705
Conversion mode, speed mode 3, gain = 0.5 to 2 540 570
Conversion mode, speed mode 3, gain = 4 and 5 640 680
Conversion mode, speed mode 3, gain = 8 to 50 870 920
Conversion mode, speed mode 3, gain = 64 to 256 1090 1140
ADDITIONAL ANALOG SUPPLY CURRENTS PER FUNCTION (AVDD = 3.3V, VREF = 2.5V)
IAVDD Analog supply current Internal voltage reference, speed mode 0 4.5 6 µA
Internal voltage reference, speed mode 1 25 28
Internal voltage reference, speed mode 2 35 40
Internal voltage reference, speed mode 3 65 75
Either REFP or REFN buffer enabled, speed mode 0
 4.5 6
Either REFP or REFN buffer enabled, speed mode 1 25 28
Either REFP or REFN buffer enabled, speed mode 2 35 40
Either REFP or REFN buffer enabled, speed mode 3 65 75
Both REFP and REFN buffers enabled, speed mode 0 6.5 9
Both REFP and REFN buffers enabled, speed mode 1 33 39
Both REFP and REFN buffers enabled, speed mode 2 51 60
Both REFP and REFN buffers enabled, speed mode 3 106 124
IDAC overhead, IDAC unit current = 1µA 4 6
IDAC overhead, IDAC unit current = 10µA 16 28
DIGITAL SUPPLY CURRENTS (DVDD = 3.3V, All Data Rates, SPI Not Active)
IDVDD Digital supply current Power-down mode 1.6 6.5 µA
Standby mode, speed mode 0 8 13
Standby mode, speed mode 1 20 26
Standby mode, speed mode 2 26 33
Standby mode, speed mode 3 40 47
Conversion mode, speed mode 0 9 16
Conversion mode, speed mode 1 30 38
Conversion mode, speed mode 2 48 56
Conversion mode, speed mode 3 82 92
ANALOG SUPPLY CURRENTS (AVDD = 1.8V, External Reference, Reference Buffers Disabled, IDACs Disabled, All Data Rates, VIN = 0V)
IAVDD Analog supply current Power-down mode 0.2 2 µA
Standby mode 8 14
Conversion mode, speed mode 0, gain = 0.5 to 2 48 55
Conversion mode, speed mode 0, gain = 4 and 5 51 58
Conversion mode, speed mode 0, gain = 8 to 50 57 64
Conversion mode, speed mode 0, gain = 64 to 256 53 60
Conversion mode, speed mode 1, gain = 0.5 to 2 120 130
Conversion mode, speed mode 1, gain = 4 and 5 140 155
Conversion mode, speed mode 1, gain = 8 to 50 190 205
Conversion mode, speed mode 1, gain = 64 to 256 240 260
Conversion mode, speed mode 2, gain = 0.5 to 2 285 305
Conversion mode, speed mode 2, gain = 4 and 5 325 345
Conversion mode, speed mode 2, gain = 8 to 50 420 445
Conversion mode, speed mode 2, gain = 64 to 256 635 670
Conversion mode, speed mode 3, gain = 0.5 to 2 485 515
Conversion mode, speed mode 3, gain = 4 and 5 580 620
Conversion mode, speed mode 3, gain = 8 to 50 810 860
Conversion mode, speed mode 3, gain = 64 to 256 1020 1080
ADDITIONAL ANALOG SUPPLY CURRENTS PER FUNCTION (AVDD = 1.8V, VREF = 1.25V)
IAVDD Analog supply current Internal voltage reference, speed mode 0 3.5 5 µA
Internal voltage reference, speed mode 1 16 20
Internal voltage reference, speed mode 2 26 31
Internal voltage reference, speed mode 3 56 66
Either REFP or REFN buffer enabled, speed mode 0
 3.5 5
Either REFP or REFN buffer enabled, speed mode 1 16 20
Either REFP or REFN buffer enabled, speed mode 2 26 31
Either REFP or REFN buffer enabled, speed mode 3 56 66
Both REFP and REFN buffers enabled, speed mode 0 5.5 8
Both REFP and REFN buffers enabled, speed mode 1 25 30
Both REFP and REFN buffers enabled, speed mode 2 43 53
Both REFP and REFN buffers enabled, speed mode 3 100 120
IDAC overhead, IDAC unit current = 1µA 4 6
IDAC overhead, IDAC unit current = 10µA 16 28
DIGITAL SUPPLY CURRENTS (DVDD = 1.8V, All Data Rates, SPI Not Active)
IDVDD Digital supply current Power-down mode 1.6 6.5 µA
Standby mode, speed mode 0 7 13
Standby mode, speed mode 1 19 26
Standby mode, speed mode 2 25 33
Standby mode, speed mode 3 39 47
Conversion mode, speed mode 0 9 16
Conversion mode, speed mode 1 30 38
Conversion mode, speed mode 2 48 56
Conversion mode, speed mode 3 82 92
(1) Input currents scale with speed mode, data rate, gain, and global-chop mode settings.
(2) Current is flowing into REFP and out of REFN.
(3) Undervoltage monitor does always trip below the specified MIN value and does never trip above the specified MAX value.