SBASB22 December   2025 ADS9324

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Switching Characteristics
    8. 5.8 Timing Diagrams
  7. 6 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Analog Inputs
      2. 7.3.2  Input Clamp Protection Circuit
      3. 7.3.3  Analog Input Impedance
      4. 7.3.4  Programmable Gain Amplifier (PGA)
      5. 7.3.5  ADC Transfer Function
      6. 7.3.6  Reference
      7. 7.3.7  Open Wire Safe Mode
      8. 7.3.8  System Offset Calibration
      9. 7.3.9  System Gain Calibration
      10. 7.3.10 ADC Gain and Offset Error Calibration
      11. 7.3.11 Digital Filter
        1. 7.3.11.1 System Phase Calibration
        2. 7.3.11.2 Block Average Filter
        3. 7.3.11.3 Moving Average Filter
        4. 7.3.11.4 Low-Pass FIR Filter
      12. 7.3.12 Digital Window Comparator
      13. 7.3.13 Alarm Modes
      14. 7.3.14 Data Interface
        1. 7.3.14.1 ADC Channel Modes
        2. 7.3.14.2 Daisy Chain
        3. 7.3.14.3 Diagnostic Flags
        4. 7.3.14.4 ADC Output Data Randomizer
        5. 7.3.14.5 Test Patterns for Data Interface
        6. 7.3.14.6 Digital Output Drive Strength Control
        7. 7.3.14.7 Digital Output Delay Adjustment
    4. 7.4 Device Functional Modes
      1. 7.4.1 Reset
      2. 7.4.2 Normal Operation
      3. 7.4.3 Standby Mode
    5. 7.5 Programming
      1. 7.5.1 Register Write Operation
      2. 7.5.2 Register Read Operation
      3. 7.5.3 Initialization Example - Single Lane Mode on SDOUT
  9. 8 Register Maps
    1. 8.1 ADS93xx Common Registers
    2. 8.2 AIN1 - AIN8 Channel Registers
    3. 8.3 AIN9 - AIN16 Channel Registers
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 16-Channel, Data Acquisition System (DAQ) for Power Automation
        1. 9.2.1.1 Application Curve
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
        1. 9.4.1.1 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Mechanical Data

8.3 AIN9 - AIN16 Channel Registers

Table 8-72 lists the memory-mapped registers for the AIN9 - AIN16 Channel registers. All register offset addresses not listed in Table 8-72 should be considered as reserved locations and the register contents should not be modified.

Table 8-72 AIN9 - AIN16 Channel
AddressAcronymBit 15Bit 14Bit 13Bit 12Bit 11Bit 10Bit 9Bit 8
Bit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0
0x08PGA_CONFIG_AIN15_16CME_CORR_EN_AIN15CM_RANGE_AIN15[2:0]RESERVEDINPUT_RANGE_AIN15[2:0]
CME_CORR_EN_AIN16CM_RANGE_AIN16[2:0]RESERVEDINPUT_RANGE_AIN16[2:0]
0x09PGA_CONFIG_AIN13_14CME_CORR_EN_AIN13CM_RANGE_AIN13[2:0]RESERVEDINPUT_RANGE_AIN13[2:0]
CME_CORR_EN_AIN14CM_RANGE_AIN14[2:0]RESERVEDINPUT_RANGE_AIN14[2:0]
0x0APGA_CONFIG_AIN11_12CME_CORR_EN_AIN11CM_RANGE_AIN11[2:0]RESERVEDINPUT_RANGE_AIN11[2:0]
CME_CORR_EN_AIN12CM_RANGE_AIN12[2:0]RESERVEDINPUT_RANGE_AIN12[2:0]
0x0BPGA_CONFIG_AIN9_10CME_CORR_EN_AIN9CM_RANGE_AIN9[2:0]RESERVEDINPUT_RANGE_AIN9[2:0]
CME_CORR_EN_AIN10CM_RANGE_AIN10[2:0]RESERVEDINPUT_RANGE_AIN10[2:0]
0x0CPGA_BW_SEL_AIN9_16PGA_BW_SEL_AIN9[1:0]PGA_BW_SEL_AIN10[1:0]PGA_BW_SEL_AIN11[1:0]PGA_BW_SEL_AIN12[1:0]
PGA_BW_SEL_AIN13[1:0]PGA_BW_SEL_AIN14[1:0]PGA_BW_SEL_AIN15[1:0]PGA_BW_SEL_AIN16[1:0]
0x0DPHASE_DELAY_AIN15_16PHASE_DELAY_AIN15[7:0]
PHASE_DELAY_AIN16[7:0]
0x0EPHASE_DELAY_AIN13_14PHASE_DELAY_AIN13[7:0]
PHASE_DELAY_AIN14[7:0]
0x0FPHASE_DELAY_AIN11_12PHASE_DELAY_AIN11[7:0]
PHASE_DELAY_AIN12[7:0]
0x10PHASE_DELAY_AIN9_10PHASE_DELAY_AIN9[7:0]
PHASE_DELAY_AIN10[7:0]
0x11OFS_AIN16RESERVEDOFS_AIN16[9:0]
OFS_AIN16[9:0]
0x12OFS_AIN15RESERVEDOFS_AIN15[9:0]
OFS_AIN15[9:0]
0x13OFS_AIN14RESERVEDOFS_AIN14[9:0]
OFS_AIN14[9:0]
0x14OFS_AIN13RESERVEDOFS_AIN13[9:0]
OFS_AIN13[9:0]
0x15OFS_AIN12RESERVEDOFS_AIN12[9:0]
OFS_AIN12[9:0]
0x16OFS_AIN11RESERVEDOFS_AIN11[9:0]
OFS_AIN11[9:0]
0x17OFS_AIN10RESERVEDOFS_AIN10[9:0]
OFS_AIN10[9:0]
0x18OFS_AIN9RESERVEDOFS_AIN9[9:0]
OFS_AIN9[9:0]
0x19GAN_AIN16RESERVEDGAN_AIN16[13:0]
GAN_AIN16[13:0]
0x1AGAN_AIN15RESERVEDGAN_AIN15[13:0]
GAN_AIN15[13:0]
0x1BGAN_AIN14RESERVEDGAN_AIN14[13:0]
GAN_AIN14[13:0]
0x1CGAN_AIN13RESERVEDGAN_AIN13[13:0]
GAN_AIN13[13:0]
0x1DGAN_AIN12RESERVEDGAN_AIN12[13:0]
GAN_AIN12[13:0]
0x1EGAN_AIN11RESERVEDGAN_AIN11[13:0]
GAN_AIN11[13:0]
0x1FGAN_AIN10RESERVEDGAN_AIN10[13:0]
GAN_AIN10[13:0]
0x20GAN_AIN9RESERVEDGAN_AIN9[13:0]
GAN_AIN9[13:0]
0x21DWC_CFGDWC_STAT_RSTRESERVEDDWC_GLITCH_FILT[3:0]
DWC_EN_AIN9DWC_EN_AIN10DWC_EN_AIN11DWC_EN_AIN12DWC_EN_AIN13DWC_EN_AIN14DWC_EN_AIN15DWC_EN_AIN16
0x22DWC_TH_AIN16HIGH_TH_AIN16[7:0]
LOW_TH_AIN16[7:0]
0x23DWC_TH_AIN15HIGH_TH_AIN15[7:0]
LOW_TH_AIN15[7:0]
0x24DWC_TH_AIN14HIGH_TH_AIN14[7:0]
LOW_TH_AIN14[7:0]
0x25DWC_TH_AIN13HIGH_TH_AIN13[7:0]
LOW_TH_AIN13[7:0]
0x26DWC_TH_AIN12HIGH_TH_AIN12[7:0]
LOW_TH_AIN12[7:0]
0x27DWC_TH_AIN11HIGH_TH_AIN11[7:0]
LOW_TH_AIN11[7:0]
0x28DWC_TH_AIN10HIGH_TH_AIN10[7:0]
LOW_TH_AIN10[7:0]
0x29DWC_TH_AIN9HIGH_TH_AIN9[7:0]
LOW_TH_AIN9[7:0]
0x2ADWC_HYS_AIN15_16HYS_AIN15[7:0]
HYS_AIN16[7:0]
0x2BDWC_HYS_AIN13_14HYS_AIN13[7:0]
HYS_AIN14[7:0]
0x2CDWC_HYS_AIN11_12HYS_AIN11[7:0]
HYS_AIN12[7:0]
0x2DDWC_HYS_AIN9_10HYS_AIN9[7:0]
HYS_AIN10[7:0]
0x2ETP_CFGRESERVED
RESERVEDTP_MODE[2:0]RESERVEDTP_DIS_IDXTP_UPD_MODETP_EN
0x2FTP_AIN16TP_AIN16[15:0]
TP_AIN16[15:0]
0x30TP_AIN15TP_AIN15[15:0]
TP_AIN15[15:0]
0x31TP_AIN14TP_AIN14[15:0]
TP_AIN14[15:0]
0x32TP_AIN13TP_AIN13[15:0]
TP_AIN13[15:0]
0x33TP_AIN12TP_AIN12[15:0]
TP_AIN12[15:0]
0x34TP_AIN11TP_AIN11[15:0]
TP_AIN11[15:0]
0x35TP_AIN10TP_AIN10[15:0]
TP_AIN10[15:0]
0x36TP_AIN9TP_AIN9[15:0]
TP_AIN9[15:0]
0x37GEN_CFG5RESERVED
RESERVEDOFS_CORR_DISGAN_CORR_DIS
0x3EDWC_FLAG_AIN9_16HIGH_FLAG_AIN9HIGH_FLAG_AIN10HIGH_FLAG_AIN11HIGH_FLAG_AIN12HIGH_FLAG_AIN13HIGH_FLAG_AIN14HIGH_FLAG_AIN15HIGH_FLAG_AIN16
LOW_FLAG_AIN9LOW_FLAG_AIN10LOW_FLAG_AIN11LOW_FLAG_AIN12LOW_FLAG_AIN13LOW_FLAG_AIN14LOW_FLAG_AIN15LOW_FLAG_AIN16

Complex bit access types are encoded to fit into small table cells. Table 8-73 shows the codes that are used for access types in this section.

Table 8-73 AIN9 - AIN16 Channel Access Type Codes
Access TypeCodeDescription
Read Type
RRRead
Write Type
WWWrite
Reset or Default Value
-nValue after reset or the default value

8.3.1 PGA_CONFIG_AIN15_16 Register (Address = 0x08) [Reset = 0x0000]

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Figure 8-68 PGA_CONFIG_AIN15_16 Register
15141312111098
CME_CORR_EN_AIN15CM_RANGE_AIN15[2:0]RESERVEDINPUT_RANGE_AIN15[2:0]
R/W-0bR/W-000bR/W-0bR/W-000b
76543210
CME_CORR_EN_AIN16CM_RANGE_AIN16[2:0]RESERVEDINPUT_RANGE_AIN16[2:0]
R/W-0bR/W-000bR/W-0bR/W-000b
Table 8-74 PGA_CONFIG_AIN15_16 Register Field Descriptions
BitFieldTypeResetDescription
15CME_CORR_EN_AIN15R/W0bCommon mode error correction enable.
  • 0b = Disabled
  • 1b = Enabled
14:12CM_RANGE_AIN15[2:0]R/W000bSelect input signal type.
  • 000b = Differential (±12.5V CM Range)
  • 101b = Single ended
  • 110b = Single ended open wire safe
11RESERVEDR/W0bReserved. Do not change from the default reset value.
10:8INPUT_RANGE_AIN15[2:0]R/W000bAIN15 analog input range selection.
  • 000b = ±5V
  • 001b = Reserved
  • 010b = ±2.5V
  • 011b = ±6.25V
  • 100b = ±10V
  • 101b = ±12.5V
  • 110b = Reserved
  • 111b = Reserved
7CME_CORR_EN_AIN16R/W0bCommon mode error correction enable.
  • 0b = Disabled
  • 1b = Enabled
6:4CM_RANGE_AIN16[2:0]R/W000bSelect input signal type.
  • 000b = Differential (±12.5V CM Range)
  • 101b = Single ended
  • 110b = Single ended open wire safe
3RESERVEDR/W0bReserved. Do not change from the default reset value.
2:0INPUT_RANGE_AIN16[2:0]R/W000bAIN16 analog input range selection.
  • 000b = ±5V
  • 001b = Reserved
  • 010b = ±2.5V
  • 011b = ±6.25V
  • 100b = ±10V
  • 101b = ±12.5V
  • 110b = Reserved
  • 111b = Reserved

8.3.2 PGA_CONFIG_AIN13_14 Register (Address = 0x09) [Reset = 0x0000]

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Figure 8-69 PGA_CONFIG_AIN13_14 Register
15141312111098
CME_CORR_EN_AIN13CM_RANGE_AIN13[2:0]RESERVEDINPUT_RANGE_AIN13[2:0]
R/W-0bR/W-000bR/W-0bR/W-000b
76543210
CME_CORR_EN_AIN14CM_RANGE_AIN14[2:0]RESERVEDINPUT_RANGE_AIN14[2:0]
R/W-0bR/W-000bR/W-0bR/W-000b
Table 8-75 PGA_CONFIG_AIN13_14 Register Field Descriptions
BitFieldTypeResetDescription
15CME_CORR_EN_AIN13R/W0bCommon mode error correction enable.
  • 0b = Disabled
  • 1b = Enabled
14:12CM_RANGE_AIN13[2:0]R/W000bSelect input signal type.
  • 000b = Differential (±12.5V CM Range)
  • 101b = Single ended
  • 110b = Single ended open wire safe
11RESERVEDR/W0bReserved. Do not change from the default reset value.
10:8INPUT_RANGE_AIN13[2:0]R/W000bAIN13 analog input range selection.
  • 000b = ±5V
  • 001b = Reserved
  • 010b = ±2.5V
  • 011b = ±6.25V
  • 100b = ±10V
  • 101b = ±12.5V
  • 110b = Reserved
  • 111b = Reserved
7CME_CORR_EN_AIN14R/W0bCommon mode error correction enable.
  • 0b = Disabled
  • 1b = Enabled
6:4CM_RANGE_AIN14[2:0]R/W000bSelect input signal type.
  • 000b = Differential (±12.5V CM Range)
  • 101b = Single ended
  • 110b = Single ended open wire safe
3RESERVEDR/W0bReserved. Do not change from the default reset value.
2:0INPUT_RANGE_AIN14[2:0]R/W000bAIN14 analog input range selection.
  • 000b = ±5V
  • 001b = Reserved
  • 010b = ±2.5V
  • 011b = ±6.25V
  • 100b = ±10V
  • 101b = ±12.5V
  • 110b = Reserved
  • 111b = Reserved

8.3.3 PGA_CONFIG_AIN11_12 Register (Address = 0x0A) [Reset = 0x0000]

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Figure 8-70 PGA_CONFIG_AIN11_12 Register
15141312111098
CME_CORR_EN_AIN11CM_RANGE_AIN11[2:0]RESERVEDINPUT_RANGE_AIN11[2:0]
R/W-0bR/W-000bR/W-0bR/W-000b
76543210
CME_CORR_EN_AIN12CM_RANGE_AIN12[2:0]RESERVEDINPUT_RANGE_AIN12[2:0]
R/W-0bR/W-000bR/W-0bR/W-000b
Table 8-76 PGA_CONFIG_AIN11_12 Register Field Descriptions
BitFieldTypeResetDescription
15CME_CORR_EN_AIN11R/W0bCommon mode error correction enable.
  • 0b = Disabled
  • 1b = Enabled
14:12CM_RANGE_AIN11[2:0]R/W000bSelect input signal type.
  • 000b = Differential (±12.5V CM Range)
  • 101b = Single ended
  • 110b = Single ended open wire safe
11RESERVEDR/W0bReserved. Do not change from the default reset value.
10:8INPUT_RANGE_AIN11[2:0]R/W000bAIN11 analog input range selection.
  • 000b = ±5V
  • 001b = Reserved
  • 010b = ±2.5V
  • 011b = ±6.25V
  • 100b = ±10V
  • 101b = ±12.5V
  • 110b = Reserved
  • 111b = Reserved
7CME_CORR_EN_AIN12R/W0bCommon mode error correction enable.
  • 0b = Disabled
  • 1b = Enabled
6:4CM_RANGE_AIN12[2:0]R/W000bSelect input signal type.
  • 000b = Fully differential (±12.5V CM Range)
  • 101b = Single ended
  • 110b = Single ended open wire safe
3RESERVEDR/W0bReserved. Do not change from the default reset value.
2:0INPUT_RANGE_AIN12[2:0]R/W000bAIN12 analog input range selection.
  • 000b = ±5V
  • 001b = Reserved
  • 010b = ±2.5V
  • 011b = ±6.25V
  • 100b = ±10V
  • 101b = ±12.5V
  • 110b = Reserved
  • 111b = Reserved

8.3.4 PGA_CONFIG_AIN9_10 Register (Address = 0x0B) [Reset = 0x0000]

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Figure 8-71 PGA_CONFIG_AIN9_10 Register
15141312111098
CME_CORR_EN_AIN9CM_RANGE_AIN9[2:0]RESERVEDINPUT_RANGE_AIN9[2:0]
R/W-0bR/W-000bR/W-0bR/W-000b
76543210
CME_CORR_EN_AIN10CM_RANGE_AIN10[2:0]RESERVEDINPUT_RANGE_AIN10[2:0]
R/W-0bR/W-000bR/W-0bR/W-000b
Table 8-77 PGA_CONFIG_AIN9_10 Register Field Descriptions
BitFieldTypeResetDescription
15CME_CORR_EN_AIN9R/W0bCommon mode error correction enable.
  • 0b = Disabled
  • 1b = Enabled
14:12CM_RANGE_AIN9[2:0]R/W000bSelect input signal type.
  • 000b = Differential (±12.5V CM Range)
  • 101b = Single ended
  • 110b = Single ended open wire safe
11RESERVEDR/W0bReserved. Do not change from the default reset value.
10:8INPUT_RANGE_AIN9[2:0]R/W000bAIN9 analog input range selection.
  • 000b = ±5V
  • 001b = Reserved
  • 010b = ±2.5V
  • 011b = ±6.25V
  • 100b = ±10V
  • 101b = ±12.5V
  • 110b = Reserved
  • 111b = Reserved
7CME_CORR_EN_AIN10R/W0bCommon mode error correction enable.
  • 0b = Disabled
  • 1b = Enabled
6:4CM_RANGE_AIN10[2:0]R/W000bSelect input signal type.
  • 000b = Differential (±12.5V CM Range)
  • 101b = Single ended
  • 110b = Single ended open wire safe
3RESERVEDR/W0bReserved. Do not change from the default reset value.
2:0INPUT_RANGE_AIN10[2:0]R/W000bAIN10 analog input range selection.
  • 000b = ±5V
  • 001b = Reserved
  • 010b = ±2.5V
  • 011b = ±6.25V
  • 100b = ±10V
  • 101b = ±12.5V
  • 110b = Reserved
  • 111b = Reserved

8.3.5 PGA_BW_SEL_AIN9_16 Register (Address = 0x0C) [Reset = 0x0000]

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Figure 8-72 PGA_BW_SEL_AIN9_16 Register
15141312111098
PGA_BW_SEL_AIN9[1:0]PGA_BW_SEL_AIN10[1:0]PGA_BW_SEL_AIN11[1:0]PGA_BW_SEL_AIN12[1:0]
R/W-00bR/W-00bR/W-00bR/W-00b
76543210
PGA_BW_SEL_AIN13[1:0]PGA_BW_SEL_AIN14[1:0]PGA_BW_SEL_AIN15[1:0]PGA_BW_SEL_AIN16[1:0]
R/W-00bR/W-00bR/W-00bR/W-00b
Table 8-78 PGA_BW_SEL_AIN9_16 Register Field Descriptions
BitFieldTypeResetDescription
15:14PGA_BW_SEL_AIN9[1:0]R/W00bAIN9 analog low pass filter configuration control.
  • 00b = Low-bandwidth
  • 01b = Wide-bandwidth
  • 10b = Reserved
  • 11b = Reserved
13:12PGA_BW_SEL_AIN10[1:0]R/W00bAIN10 analog low pass filter configuration control.
  • 00b = Low-bandwidth
  • 01b = Wide-bandwidth
  • 10b = Reserved
  • 11b = Reserved
11:10PGA_BW_SEL_AIN11[1:0]R/W00bAIN11 analog low pass filter configuration control.
  • 00b = Low-bandwidth
  • 01b = Wide-bandwidth
  • 10b = Reserved
  • 11b = Reserved
9:8PGA_BW_SEL_AIN12[1:0]R/W00bAIN12 analog low pass filter configuration control.
  • 00b = Low-bandwidth
  • 01b = Wide-bandwidth
  • 10b = Reserved
  • 11b = Reserved
7:6PGA_BW_SEL_AIN13[1:0]R/W00bAIN13 analog low pass filter configuration control.
  • 00b = Low-bandwidth
  • 01b = Wide-bandwidth
  • 10b = Reserved
  • 11b = Reserved
5:4PGA_BW_SEL_AIN14[1:0]R/W00bAIN14analog low pass filter configuration control.
  • 00b = Low-bandwidth
  • 01b = Wide-bandwidth
  • 10b = Reserved
  • 11b = Reserved
3:2PGA_BW_SEL_AIN15[1:0]R/W00bAIN15 analog low pass filter configuration control.
  • 00b = Low-bandwidth
  • 01b = Wide-bandwidth
  • 10b = Reserved
  • 11b = Reserved
1:0PGA_BW_SEL_AIN16[1:0]R/W00bAIN16 analog low pass filter configuration control.
  • 00b = Low-bandwidth
  • 01b = Wide-bandwidth
  • 10b = Reserved
  • 11b = Reserved

8.3.6 PHASE_DELAY_AIN15_16 Register (Address = 0x0D) [Reset = 0x0000]

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Figure 8-73 PHASE_DELAY_AIN15_16 Register
15141312111098
PHASE_DELAY_AIN15[7:0]
R/W-00000000b
76543210
PHASE_DELAY_AIN16[7:0]
R/W-00000000b
Table 8-79 PHASE_DELAY_AIN15_16 Register Field Descriptions
BitFieldTypeResetDescription
15:8PHASE_DELAY_AIN15[7:0]R/W00000000bPhase delay = n* ADC CONVST CLK, where n is 0 to 255.
7:0PHASE_DELAY_AIN16[7:0]R/W00000000bPhase delay = n* ADC CONVST CLK, where n is 0 to 255.

8.3.7 PHASE_DELAY_AIN13_14 Register (Address = 0x0E) [Reset = 0x0000]

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Figure 8-74 PHASE_DELAY_AIN13_14 Register
15141312111098
PHASE_DELAY_AIN13[7:0]
R/W-00000000b
76543210
PHASE_DELAY_AIN14[7:0]
R/W-00000000b
Table 8-80 PHASE_DELAY_AIN13_14 Register Field Descriptions
BitFieldTypeResetDescription
15:8PHASE_DELAY_AIN13[7:0]R/W00000000bPhase delay = n* CONVST_CLK, where n is 0 to 255.
7:0PHASE_DELAY_AIN14[7:0]R/W00000000bPhase delay = n* CONVST_CLK, where n is 0 to 255.

8.3.8 PHASE_DELAY_AIN11_12 Register (Address = 0x0F) [Reset = 0x0000]

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Figure 8-75 PHASE_DELAY_AIN11_12 Register
15141312111098
PHASE_DELAY_AIN11[7:0]
R/W-00000000b
76543210
PHASE_DELAY_AIN12[7:0]
R/W-00000000b
Table 8-81 PHASE_DELAY_AIN11_12 Register Field Descriptions
BitFieldTypeResetDescription
15:8PHASE_DELAY_AIN11[7:0]R/W00000000bPhase delay = n* CONVST_CLK, where n is 0 to 255.
7:0PHASE_DELAY_AIN12[7:0]R/W00000000bPhase delay = n* CONVST_CLK, where n is 0 to 255.

8.3.9 PHASE_DELAY_AIN9_10 Register (Address = 0x10) [Reset = 0x0000]

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Figure 8-76 PHASE_DELAY_AIN9_10 Register
15141312111098
PHASE_DELAY_AIN9[7:0]
R/W-00000000b
76543210
PHASE_DELAY_AIN10[7:0]
R/W-00000000b
Table 8-82 PHASE_DELAY_AIN9_10 Register Field Descriptions
BitFieldTypeResetDescription
15:8PHASE_DELAY_AIN9[7:0]R/W00000000bPhase delay = n* CONVST_CLK, where n is 0 to 255.
7:0PHASE_DELAY_AIN10[7:0]R/W00000000bPhase delay = n* CONVST_CLK, where n is 0 to 255.

8.3.10 OFS_AIN16 Register (Address = 0x11) [Reset = 0x0000]

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Figure 8-77 OFS_AIN16 Register
15141312111098
RESERVEDOFS_AIN16[9:0]
R/W-000000bR/W-0000000000b
76543210
OFS_AIN16[9:0]
R/W-0000000000b
Table 8-83 OFS_AIN16 Register Field Descriptions
BitFieldTypeResetDescription
15:10RESERVEDR/W000000bReserved. Do not change from the default reset value.
9:0OFS_AIN16[9:0]R/W0000000000bOffset correction register for AIN16.
The offset value is in two's complement representation. The offset operation precedes the gain operation.

8.3.11 OFS_AIN15 Register (Address = 0x12) [Reset = 0x0000]

Return to the Summary Table.

Figure 8-78 OFS_AIN15 Register
15141312111098
RESERVEDOFS_AIN15[9:0]
R/W-000000bR/W-0000000000b
76543210
OFS_AIN15[9:0]
R/W-0000000000b
Table 8-84 OFS_AIN15 Register Field Descriptions
BitFieldTypeResetDescription
15:10RESERVEDR/W000000bReserved. Do not change from the default reset value.
9:0OFS_AIN15[9:0]R/W0000000000bOffset correction register for AIN15.
The offset value is in two's complement representation. The offset operation precedes the gain operation.

8.3.12 OFS_AIN14 Register (Address = 0x13) [Reset = 0x0000]

Return to the Summary Table.

Figure 8-79 OFS_AIN14 Register
15141312111098
RESERVEDOFS_AIN14[9:0]
R/W-000000bR/W-0000000000b
76543210
OFS_AIN14[9:0]
R/W-0000000000b
Table 8-85 OFS_AIN14 Register Field Descriptions
BitFieldTypeResetDescription
15:10RESERVEDR/W000000bReserved. Do not change from the default reset value.
9:0OFS_AIN14[9:0]R/W0000000000bOffset correction register for AIN14.
The offset value is in two's complement representation. The offset operation precedes the gain operation.

8.3.13 OFS_AIN13 Register (Address = 0x14) [Reset = 0x0000]

Return to the Summary Table.

Figure 8-80 OFS_AIN13 Register
15141312111098
RESERVEDOFS_AIN13[9:0]
R/W-000000bR/W-0000000000b
76543210
OFS_AIN13[9:0]
R/W-0000000000b
Table 8-86 OFS_AIN13 Register Field Descriptions
BitFieldTypeResetDescription
15:10RESERVEDR/W000000bReserved. Do not change from the default reset value.
9:0OFS_AIN13[9:0]R/W0000000000bOffset correction register for AIN13.
The offset value is in two's complement representation. The offset operation precedes the gain operation.

8.3.14 OFS_AIN12 Register (Address = 0x15) [Reset = 0x0000]

Return to the Summary Table.

Figure 8-81 OFS_AIN12 Register
15141312111098
RESERVEDOFS_AIN12[9:0]
R/W-000000bR/W-0000000000b
76543210
OFS_AIN12[9:0]
R/W-0000000000b
Table 8-87 OFS_AIN12 Register Field Descriptions
BitFieldTypeResetDescription
15:10RESERVEDR/W000000bReserved. Do not change from the default reset value.
9:0OFS_AIN12[9:0]R/W0000000000bOffset correction register for AIN12.
The offset value is in two's complement representation. The offset operation precedes the gain operation.

8.3.15 OFS_AIN11 Register (Address = 0x16) [Reset = 0x0000]

Return to the Summary Table.

Figure 8-82 OFS_AIN11 Register
15141312111098
RESERVEDOFS_AIN11[9:0]
R/W-000000bR/W-0000000000b
76543210
OFS_AIN11[9:0]
R/W-0000000000b
Table 8-88 OFS_AIN11 Register Field Descriptions
BitFieldTypeResetDescription
15:10RESERVEDR/W000000bReserved. Do not change from the default reset value.
9:0OFS_AIN11[9:0]R/W0000000000bOffset correction register for AIN11.
The offset value is in two's complement representation. The offset operation precedes the gain operation.

8.3.16 OFS_AIN10 Register (Address = 0x17) [Reset = 0x0000]

Return to the Summary Table.

Figure 8-83 OFS_AIN10 Register
15141312111098
RESERVEDOFS_AIN10[9:0]
R/W-000000bR/W-0000000000b
76543210
OFS_AIN10[9:0]
R/W-0000000000b
Table 8-89 OFS_AIN10 Register Field Descriptions
BitFieldTypeResetDescription
15:10RESERVEDR/W000000bReserved. Do not change from the default reset value.
9:0OFS_AIN10[9:0]R/W0000000000bOffset correction register for AIN10.
The offset value is in two's complement representation. The offset operation precedes the gain operation.

8.3.17 OFS_AIN9 Register (Address = 0x18) [Reset = 0x0000]

Return to the Summary Table.

Figure 8-84 OFS_AIN9 Register
15141312111098
RESERVEDOFS_AIN9[9:0]
R/W-000000bR/W-0000000000b
76543210
OFS_AIN9[9:0]
R/W-0000000000b
Table 8-90 OFS_AIN9 Register Field Descriptions
BitFieldTypeResetDescription
15:10RESERVEDR/W000000bReserved. Do not change from the default reset value.
9:0OFS_AIN9[9:0]R/W0000000000bOffset correction register for AIN9.
The offset value is in two's complement representation. The offset operation precedes the gain operation.

8.3.18 GAN_AIN16 Register (Address = 0x19) [Reset = 0x0000]

Return to the Summary Table.

Figure 8-85 GAN_AIN16 Register
15141312111098
RESERVEDGAN_AIN16[13:0]
R/W-00bR/W-00000000000000b
76543210
GAN_AIN16[13:0]
R/W-00000000000000b
Table 8-91 GAN_AIN16 Register Field Descriptions
BitFieldTypeResetDescription
15:14RESERVEDR/W00bReserved. Do not change from the default reset value.
13:0GAN_AIN16[13:0]R/W00000000000000bGain correction register for AIN16.
The gain correction value is in two's complement representation, and is done after offset operation. During gain operation, the conversion data are multiplied by (1 + GAN_AINn[13:0] / 10000h).

8.3.19 GAN_AIN15 Register (Address = 0x1A) [Reset = 0x0000]

Return to the Summary Table.

Figure 8-86 GAN_AIN15 Register
15141312111098
RESERVEDGAN_AIN15[13:0]
R/W-00bR/W-00000000000000b
76543210
GAN_AIN15[13:0]
R/W-00000000000000b
Table 8-92 GAN_AIN15 Register Field Descriptions
BitFieldTypeResetDescription
15:14RESERVEDR/W00bReserved. Do not change from the default reset value.
13:0GAN_AIN15[13:0]R/W00000000000000bGain correction register for AIN15.
The gain correction value is in two's complement representation, and is done after offset operation. During gain operation, the conversion data are multiplied by (1 + GAN_AINn[13:0] / 10000h).

8.3.20 GAN_AIN14 Register (Address = 0x1B) [Reset = 0x0000]

Return to the Summary Table.

Figure 8-87 GAN_AIN14 Register
15141312111098
RESERVEDGAN_AIN14[13:0]
R/W-00bR/W-00000000000000b
76543210
GAN_AIN14[13:0]
R/W-00000000000000b
Table 8-93 GAN_AIN14 Register Field Descriptions
BitFieldTypeResetDescription
15:14RESERVEDR/W00bReserved. Do not change from the default reset value.
13:0GAN_AIN14[13:0]R/W00000000000000bGain correction register for AIN14.
The gain correction value is in two's complement representation, and is done after offset operation. During gain operation, the conversion data are multiplied by (1 + GAN_AINn[13:0] / 10000h).

8.3.21 GAN_AIN13 Register (Address = 0x1C) [Reset = 0x0000]

Return to the Summary Table.

Figure 8-88 GAN_AIN13 Register
15141312111098
RESERVEDGAN_AIN13[13:0]
R/W-00bR/W-00000000000000b
76543210
GAN_AIN13[13:0]
R/W-00000000000000b
Table 8-94 GAN_AIN13 Register Field Descriptions
BitFieldTypeResetDescription
15:14RESERVEDR/W00bReserved. Do not change from the default reset value.
13:0GAN_AIN13[13:0]R/W00000000000000bGain correction register for AIN13.
The gain correction value is in two's complement representation, and is done after offset operation. During gain operation, the conversion data are multiplied by (1 + GAN_AINn[13:0] / 10000h).

8.3.22 GAN_AIN12 Register (Address = 0x1D) [Reset = 0x0000]

Return to the Summary Table.

Figure 8-89 GAN_AIN12 Register
15141312111098
RESERVEDGAN_AIN12[13:0]
R/W-00bR/W-00000000000000b
76543210
GAN_AIN12[13:0]
R/W-00000000000000b
Table 8-95 GAN_AIN12 Register Field Descriptions
BitFieldTypeResetDescription
15:14RESERVEDR/W00bReserved. Do not change from the default reset value.
13:0GAN_AIN12[13:0]R/W00000000000000bGain correction register for AIN12.
The gain correction value is in two's complement representation, and is done after offset operation. During gain operation, the conversion data are multiplied by (1 + GAN_AINn[13:0] / 10000h).

8.3.23 GAN_AIN11 Register (Address = 0x1E) [Reset = 0x0000]

Return to the Summary Table.

Figure 8-90 GAN_AIN11 Register
15141312111098
RESERVEDGAN_AIN11[13:0]
R/W-00bR/W-00000000000000b
76543210
GAN_AIN11[13:0]
R/W-00000000000000b
Table 8-96 GAN_AIN11 Register Field Descriptions
BitFieldTypeResetDescription
15:14RESERVEDR/W00bReserved. Do not change from the default reset value.
13:0GAN_AIN11[13:0]R/W00000000000000bGain correction register for AIN11.
The gain correction value is in two's complement representation, and is done after offset operation. During gain operation, the conversion data are multiplied by (1 + GAN_AINn[13:0] / 10000h).

8.3.24 GAN_AIN10 Register (Address = 0x1F) [Reset = 0x0000]

Return to the Summary Table.

Figure 8-91 GAN_AIN10 Register
15141312111098
RESERVEDGAN_AIN10[13:0]
R/W-00bR/W-00000000000000b
76543210
GAN_AIN10[13:0]
R/W-00000000000000b
Table 8-97 GAN_AIN10 Register Field Descriptions
BitFieldTypeResetDescription
15:14RESERVEDR/W00bReserved. Do not change from the default reset value.
13:0GAN_AIN10[13:0]R/W00000000000000bGain correction register for AIN10.
The gain correction value is in two's complement representation, and is done after offset operation. During gain operation, the conversion data are multiplied by (1 + GAN_AINn[13:0] / 10000h).

8.3.25 GAN_AIN9 Register (Address = 0x20) [Reset = 0x0000]

Return to the Summary Table.

Figure 8-92 GAN_AIN9 Register
15141312111098
RESERVEDGAN_AIN9[13:0]
R/W-00bR/W-00000000000000b
76543210
GAN_AIN9[13:0]
R/W-00000000000000b
Table 8-98 GAN_AIN9 Register Field Descriptions
BitFieldTypeResetDescription
15:14RESERVEDR/W00bReserved. Do not change from the default reset value.
13:0GAN_AIN9[13:0]R/W00000000000000bGain correction register for AIN9.
The gain correction value is in two's complement representation, and is done after offset operation. During gain operation, the conversion data are multiplied by (1 + GAN_AINn[13:0] / 10000h).

8.3.26 DWC_CFG Register (Address = 0x21) [Reset = 0x0000]

Return to the Summary Table.

Figure 8-93 DWC_CFG Register
15141312111098
DWC_STAT_RSTRESERVEDDWC_GLITCH_FILT[3:0]
R/W-0bR/W-000bR/W-0000b
76543210
DWC_EN_AIN9DWC_EN_AIN10DWC_EN_AIN11DWC_EN_AIN12DWC_EN_AIN13DWC_EN_AIN14DWC_EN_AIN15DWC_EN_AIN16
R/W-0bR/W-0bR/W-0bR/W-0bR/W-0bR/W-0bR/W-0bR/W-0b
Table 8-99 DWC_CFG Register Field Descriptions
BitFieldTypeResetDescription
15DWC_STAT_RSTR/W0bDigital window comparator reset control. Write 1'b to reset the DWC status flags.
14:12RESERVEDR/W000bReserved. Do not change from the default reset value.
11:8DWC_GLITCH_FILT[3:0]R/W0000bDigital window comparator glitch rejection filter control.
Comparator flag is set only when ADC data exceeds the threshold for consecutive number of DWC_GLITCH_FILT[3:0] cycles.
7DWC_EN_AIN9R/W0bDigital window comparator enable.
  • 0b = Disabled
  • 1b = Enabled
6DWC_EN_AIN10R/W0bDigital window comparator enable.
  • 0b = Disabled
  • 1b = Enabled
5DWC_EN_AIN11R/W0bDigital window comparator enable.
  • 0b = Disabled
  • 1b = Enabled
4DWC_EN_AIN12R/W0bDigital window comparator enable.
  • 0b = Disabled
  • 1b = Enabled
3DWC_EN_AIN13R/W0bDigital window comparator enable.
  • 0b = Disabled
  • 1b = Enabled
2DWC_EN_AIN14R/W0bDigital window comparator enable.
  • 0b = Disabled
  • 1b = Enabled
1DWC_EN_AIN15R/W0bDigital window comparator enable.
  • 0b = Disabled
  • 1b = Enabled
0DWC_EN_AIN16R/W0bDigital window comparator enable.
  • 0b = Disabled
  • 1b = Enabled

8.3.27 DWC_TH_AIN16 Register (Address = 0x22) [Reset = 0xFF00]

Return to the Summary Table.

Figure 8-94 DWC_TH_AIN16 Register
15141312111098
HIGH_TH_AIN16[7:0]
R/W-11111111b
76543210
LOW_TH_AIN16[7:0]
R/W-00000000b
Table 8-100 DWC_TH_AIN16 Register Field Descriptions
BitFieldTypeResetDescription
15:8HIGH_TH_AIN16[7:0]R/W11111111bMSB aligned high threshold for analog input. These bits are compared with top 8 bits of ADC conversion result.
7:0LOW_TH_AIN16[7:0]R/W00000000bMSB aligned low threshold for analog input. These bits are compared with top 8 bits of ADC conversion result.

8.3.28 DWC_TH_AIN15 Register (Address = 0x23) [Reset = 0xFF00]

Return to the Summary Table.

Figure 8-95 DWC_TH_AIN15 Register
15141312111098
HIGH_TH_AIN15[7:0]
R/W-11111111b
76543210
LOW_TH_AIN15[7:0]
R/W-00000000b
Table 8-101 DWC_TH_AIN15 Register Field Descriptions
BitFieldTypeResetDescription
15:8HIGH_TH_AIN15[7:0]R/W11111111bMSB aligned high threshold for analog input. These bits are compared with top 8 bits of ADC conversion result.
7:0LOW_TH_AIN15[7:0]R/W00000000bMSB aligned low threshold for analog input. These bits are compared with top 8 bits of ADC conversion result.

8.3.29 DWC_TH_AIN14 Register (Address = 0x24) [Reset = 0xFF00]

Return to the Summary Table.

Figure 8-96 DWC_TH_AIN14 Register
15141312111098
HIGH_TH_AIN14[7:0]
R/W-11111111b
76543210
LOW_TH_AIN14[7:0]
R/W-00000000b
Table 8-102 DWC_TH_AIN14 Register Field Descriptions
BitFieldTypeResetDescription
15:8HIGH_TH_AIN14[7:0]R/W11111111bMSB aligned high threshold for analog input. These bits are compared with top 8 bits of ADC conversion result.
7:0LOW_TH_AIN14[7:0]R/W00000000bMSB aligned low threshold for analog input. These bits are compared with top 8 bits of ADC conversion result.

8.3.30 DWC_TH_AIN13 Register (Address = 0x25) [Reset = 0xFF00]

Return to the Summary Table.

Figure 8-97 DWC_TH_AIN13 Register
15141312111098
HIGH_TH_AIN13[7:0]
R/W-11111111b
76543210
LOW_TH_AIN13[7:0]
R/W-00000000b
Table 8-103 DWC_TH_AIN13 Register Field Descriptions
BitFieldTypeResetDescription
15:8HIGH_TH_AIN13[7:0]R/W11111111bMSB aligned high threshold for analog input. These bits are compared with top 8 bits of ADC conversion result.
7:0LOW_TH_AIN13[7:0]R/W00000000bMSB aligned low threshold for analog input. These bits are compared with top 8 bits of ADC conversion result.

8.3.31 DWC_TH_AIN12 Register (Address = 0x26) [Reset = 0xFF00]

Return to the Summary Table.

Figure 8-98 DWC_TH_AIN12 Register
15141312111098
HIGH_TH_AIN12[7:0]
R/W-11111111b
76543210
LOW_TH_AIN12[7:0]
R/W-00000000b
Table 8-104 DWC_TH_AIN12 Register Field Descriptions
BitFieldTypeResetDescription
15:8HIGH_TH_AIN12[7:0]R/W11111111bMSB aligned high threshold for analog input. These bits are compared with top 8 bits of ADC conversion result.
7:0LOW_TH_AIN12[7:0]R/W00000000bMSB aligned low threshold for analog input. These bits are compared with top 8 bits of ADC conversion result.

8.3.32 DWC_TH_AIN11 Register (Address = 0x27) [Reset = 0xFF00]

Return to the Summary Table.

Figure 8-99 DWC_TH_AIN11 Register
15141312111098
HIGH_TH_AIN11[7:0]
R/W-11111111b
76543210
LOW_TH_AIN11[7:0]
R/W-00000000b
Table 8-105 DWC_TH_AIN11 Register Field Descriptions
BitFieldTypeResetDescription
15:8HIGH_TH_AIN11[7:0]R/W11111111bMSB aligned high threshold for analog input. These bits are compared with top 8 bits of ADC conversion result.
7:0LOW_TH_AIN11[7:0]R/W00000000bMSB aligned low threshold for analog input. These bits are compared with top 8 bits of ADC conversion result.

8.3.33 DWC_TH_AIN10 Register (Address = 0x28) [Reset = 0xFF00]

Return to the Summary Table.

Figure 8-100 DWC_TH_AIN10 Register
15141312111098
HIGH_TH_AIN10[7:0]
R/W-11111111b
76543210
LOW_TH_AIN10[7:0]
R/W-00000000b
Table 8-106 DWC_TH_AIN10 Register Field Descriptions
BitFieldTypeResetDescription
15:8HIGH_TH_AIN10[7:0]R/W11111111bMSB aligned high threshold for analog input. These bits are compared with top 8 bits of ADC conversion result.
7:0LOW_TH_AIN10[7:0]R/W00000000bMSB aligned low threshold for analog input. These bits are compared with top 8 bits of ADC conversion result.

8.3.34 DWC_TH_AIN9 Register (Address = 0x29) [Reset = 0xFF00]

Return to the Summary Table.

Figure 8-101 DWC_TH_AIN9 Register
15141312111098
HIGH_TH_AIN9[7:0]
R/W-11111111b
76543210
LOW_TH_AIN9[7:0]
R/W-00000000b
Table 8-107 DWC_TH_AIN9 Register Field Descriptions
BitFieldTypeResetDescription
15:8HIGH_TH_AIN9[7:0]R/W11111111bMSB aligned high threshold for analog input. These bits are compared with top 8 bits of ADC conversion result.
7:0LOW_TH_AIN9[7:0]R/W00000000bMSB aligned low threshold for analog input. These bits are compared with top 8 bits of ADC conversion result.

8.3.35 DWC_HYS_AIN15_16 Register (Address = 0x2A) [Reset = 0x0000]

Return to the Summary Table.

Figure 8-102 DWC_HYS_AIN15_16 Register
15141312111098
HYS_AIN15[7:0]
R/W-00000000b
76543210
HYS_AIN16[7:0]
R/W-00000000b
Table 8-108 DWC_HYS_AIN15_16 Register Field Descriptions
BitFieldTypeResetDescription
15:8HYS_AIN15[7:0]R/W00000000b8-bit hysteresis for high and low thresholds.
7:0HYS_AIN16[7:0]R/W00000000b8-bit hysteresis for high and low thresholds.

8.3.36 DWC_HYS_AIN13_14 Register (Address = 0x2B) [Reset = 0xFF00]

Return to the Summary Table.

Figure 8-103 DWC_HYS_AIN13_14 Register
15141312111098
HYS_AIN13[7:0]
R/W-11111111b
76543210
HYS_AIN14[7:0]
R/W-00000000b
Table 8-109 DWC_HYS_AIN13_14 Register Field Descriptions
BitFieldTypeResetDescription
15:8HYS_AIN13[7:0]R/W11111111b8-bit hysteresis for high and low thresholds.
7:0HYS_AIN14[7:0]R/W00000000b8-bit hysteresis for high and low thresholds.

8.3.37 DWC_HYS_AIN11_12 Register (Address = 0x2C) [Reset = 0xFF00]

Return to the Summary Table.

Figure 8-104 DWC_HYS_AIN11_12 Register
15141312111098
HYS_AIN11[7:0]
R/W-11111111b
76543210
HYS_AIN12[7:0]
R/W-00000000b
Table 8-110 DWC_HYS_AIN11_12 Register Field Descriptions
BitFieldTypeResetDescription
15:8HYS_AIN11[7:0]R/W11111111b8-bit hysteresis for high and low thresholds.
7:0HYS_AIN12[7:0]R/W00000000b8-bit hysteresis for high and low thresholds.

8.3.38 DWC_HYS_AIN9_10 Register (Address = 0x2D) [Reset = 0xFF00]

Return to the Summary Table.

Figure 8-105 DWC_HYS_AIN9_10 Register
15141312111098
HYS_AIN9[7:0]
R/W-11111111b
76543210
HYS_AIN10[7:0]
R/W-00000000b
Table 8-111 DWC_HYS_AIN9_10 Register Field Descriptions
BitFieldTypeResetDescription
15:8HYS_AIN9[7:0]R/W11111111b8-bit hysteresis for high and low thresholds.
7:0HYS_AIN10[7:0]R/W00000000b8-bit hysteresis for high and low thresholds.

8.3.39 TP_CFG Register (Address = 0x2E) [Reset = 0x0000]

Return to the Summary Table.

Figure 8-106 TP_CFG Register
15141312111098
RESERVED
R/W-000000000b
76543210
RESERVEDTP_MODE[2:0]RESERVEDTP_DIS_IDXTP_UPD_MODETP_EN
R/W-000000000bR/W-000bR/W-0bR/W-0bR/W-0bR/W-0b
Table 8-112 TP_CFG Register Field Descriptions
BitFieldTypeResetDescription
15:7RESERVEDR/W000000000bReserved. Do not change from the default reset value.
6:4TP_MODE[2:0]R/W000bTest pattern mode selection.
  • 000b = Constant pattern
  • 001b = Reserved
  • 010b = Ramp pattern
  • 011b = Reserved
  • 100b = Reserved
  • 101b = Reserved
3RESERVEDR/W0bReserved. Do not change from the default reset value.
2TP_DIS_IDXR/W0bWhen 1'b channel index insertion in test pattern is disabled.
1TP_UPD_MODER/W0bTest pattern increment mode.
  • 0b = Increment happens at channel frame boundary.
  • 1b = Increment happens at every CONVST.
0TP_ENR/W0bTest pattern enable for AIN9 to AIN16.
  • 0b = ADC conversion result is launched on the data interface
  • 1b = Digital test pattern is launched on the data interface

8.3.40 TP_AIN16 Register (Address = 0x2F) [Reset = 0x0000]

Return to the Summary Table.

Figure 8-107 TP_AIN16 Register
15141312111098
TP_AIN16[15:0]
R/W-0000000000000000b
76543210
TP_AIN16[15:0]
R/W-0000000000000000b
Table 8-113 TP_AIN16 Register Field Descriptions
BitFieldTypeResetDescription
15:0TP_AIN16[15:0]R/W0000000000000000bFixed 16 bit pattern for AIN16. In the ramp pattern mode, TP_AIN16 controls step size for AIN9 to AIN16.

8.3.41 TP_AIN15 Register (Address = 0x30) [Reset = 0x0000]

Return to the Summary Table.

Figure 8-108 TP_AIN15 Register
15141312111098
TP_AIN15[15:0]
R/W-0000000000000000b
76543210
TP_AIN15[15:0]
R/W-0000000000000000b
Table 8-114 TP_AIN15 Register Field Descriptions
BitFieldTypeResetDescription
15:0TP_AIN15[15:0]R/W0000000000000000bFixed 16 bit pattern for AIN15.

8.3.42 TP_AIN14 Register (Address = 0x31) [Reset = 0x0000]

Return to the Summary Table.

Figure 8-109 TP_AIN14 Register
15141312111098
TP_AIN14[15:0]
R/W-0000000000000000b
76543210
TP_AIN14[15:0]
R/W-0000000000000000b
Table 8-115 TP_AIN14 Register Field Descriptions
BitFieldTypeResetDescription
15:0TP_AIN14[15:0]R/W0000000000000000bFixed 16 bit pattern for AIN14.

8.3.43 TP_AIN13 Register (Address = 0x32) [Reset = 0x0000]

Return to the Summary Table.

Figure 8-110 TP_AIN13 Register
15141312111098
TP_AIN13[15:0]
R/W-0000000000000000b
76543210
TP_AIN13[15:0]
R/W-0000000000000000b
Table 8-116 TP_AIN13 Register Field Descriptions
BitFieldTypeResetDescription
15:0TP_AIN13[15:0]R/W0000000000000000bFixed 16 bit pattern for AIN13.

8.3.44 TP_AIN12 Register (Address = 0x33) [Reset = 0x0000]

Return to the Summary Table.

Figure 8-111 TP_AIN12 Register
15141312111098
TP_AIN12[15:0]
R/W-0000000000000000b
76543210
TP_AIN12[15:0]
R/W-0000000000000000b
Table 8-117 TP_AIN12 Register Field Descriptions
BitFieldTypeResetDescription
15:0TP_AIN12[15:0]R/W0000000000000000bFixed 16 bit pattern for AIN12.

8.3.45 TP_AIN11 Register (Address = 0x34) [Reset = 0x0000]

Return to the Summary Table.

Figure 8-112 TP_AIN11 Register
15141312111098
TP_AIN11[15:0]
R/W-0000000000000000b
76543210
TP_AIN11[15:0]
R/W-0000000000000000b
Table 8-118 TP_AIN11 Register Field Descriptions
BitFieldTypeResetDescription
15:0TP_AIN11[15:0]R/W0000000000000000bFixed 16 bit pattern for AIN11.

8.3.46 TP_AIN10 Register (Address = 0x35) [Reset = 0x0000]

Return to the Summary Table.

Figure 8-113 TP_AIN10 Register
15141312111098
TP_AIN10[15:0]
R/W-0000000000000000b
76543210
TP_AIN10[15:0]
R/W-0000000000000000b
Table 8-119 TP_AIN10 Register Field Descriptions
BitFieldTypeResetDescription
15:0TP_AIN10[15:0]R/W0000000000000000bFixed 16 bit pattern for AIN10.

8.3.47 TP_AIN9 Register (Address = 0x36) [Reset = 0x0000]

Return to the Summary Table.

Figure 8-114 TP_AIN9 Register
15141312111098
TP_AIN9[15:0]
R/W-0000000000000000b
76543210
TP_AIN9[15:0]
R/W-0000000000000000b
Table 8-120 TP_AIN9 Register Field Descriptions
BitFieldTypeResetDescription
15:0TP_AIN9[15:0]R/W0000000000000000bFixed 16 bit pattern for AIN9.

8.3.48 GEN_CFG5 Register (Address = 0x37) [Reset = 0x0000]

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Figure 8-115 GEN_CFG5 Register
15141312111098
RESERVED
R/W-00000000000b
76543210
RESERVEDRESERVEDRESERVEDOFS_CORR_DISGAN_CORR_DIS
R/W-00000000000bR/W-0bR/W-00bR/W-0bR/W-0b
Table 8-121 GEN_CFG5 Register Field Descriptions
BitFieldTypeResetDescription
15:5RESERVEDR/W00000000000bReserved. Do not change from the default reset value.
4RESERVEDR/W0bReserved. Do not change from the default reset value.
3:2RESERVEDR/W00bReserved. Do not change from the default reset value.
1OFS_CORR_DISR/W0bSystem offset correction disable for AIN9 to AIN16.
  • 0b = Enabled
  • 1b = Disabled
0GAN_CORR_DISR/W0bSystem gain correction disable for AIN9 to AIN16.
  • 0b = Enabled
  • 1b = Disabled

8.3.49 DWC_FLAG_AIN9_16 Register (Address = 0x3E) [Reset = 0x0000]

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Figure 8-116 DWC_FLAG_AIN9_16 Register
15141312111098
HIGH_FLAG_AIN9HIGH_FLAG_AIN10HIGH_FLAG_AIN11HIGH_FLAG_AIN12HIGH_FLAG_AIN13HIGH_FLAG_AIN14HIGH_FLAG_AIN15HIGH_FLAG_AIN16
R-0bR-0bR-0bR-0bR-0bR-0bR-0bR-0b
76543210
LOW_FLAG_AIN9LOW_FLAG_AIN10LOW_FLAG_AIN11LOW_FLAG_AIN12LOW_FLAG_AIN13LOW_FLAG_AIN14LOW_FLAG_AIN15LOW_FLAG_AIN16
R-0bR-0bR-0bR-0bR-0bR-0bR-0bR-0b
Table 8-122 DWC_FLAG_AIN9_16 Register Field Descriptions
BitFieldTypeResetDescription
15HIGH_FLAG_AIN9R0bDigital window comparator high flag for AIN9.
14HIGH_FLAG_AIN10R0bDigital window comparator high flag for AIN10.
13HIGH_FLAG_AIN11R0bDigital window comparator high flag for AIN11.
12HIGH_FLAG_AIN12R0bDigital window comparator high flag for AIN12.
11HIGH_FLAG_AIN13R0bDigital window comparator high flag for AIN13.
10HIGH_FLAG_AIN14R0bDigital window comparator high flag for AIN14.
9HIGH_FLAG_AIN15R0bDigital window comparator high flag for AIN15.
8HIGH_FLAG_AIN16R0bDigital window comparator high flag for AIN16.
7LOW_FLAG_AIN9R0bDigital window comparator low flag for AIN9.
6LOW_FLAG_AIN10R0bDigital window comparator low flag for AIN10.
5LOW_FLAG_AIN11R0bDigital window comparator low flag for AIN11.
4LOW_FLAG_AIN12R0bDigital window comparator low flag for AIN12.
3LOW_FLAG_AIN13R0bDigital window comparator low flag for AIN13.
2LOW_FLAG_AIN14R0bDigital window comparator low flag for AIN14.
1LOW_FLAG_AIN15R0bDigital window comparator low flag for AIN15.
0LOW_FLAG_AIN16R0bDigital window comparator low flag for AIN16.