SBASB22 December   2025 ADS9324

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Switching Characteristics
    8. 5.8 Timing Diagrams
  7. 6 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Analog Inputs
      2. 7.3.2  Input Clamp Protection Circuit
      3. 7.3.3  Analog Input Impedance
      4. 7.3.4  Programmable Gain Amplifier (PGA)
      5. 7.3.5  ADC Transfer Function
      6. 7.3.6  Reference
      7. 7.3.7  Open Wire Safe Mode
      8. 7.3.8  System Offset Calibration
      9. 7.3.9  System Gain Calibration
      10. 7.3.10 ADC Gain and Offset Error Calibration
      11. 7.3.11 Digital Filter
        1. 7.3.11.1 System Phase Calibration
        2. 7.3.11.2 Block Average Filter
        3. 7.3.11.3 Moving Average Filter
        4. 7.3.11.4 Low-Pass FIR Filter
      12. 7.3.12 Digital Window Comparator
      13. 7.3.13 Alarm Modes
      14. 7.3.14 Data Interface
        1. 7.3.14.1 ADC Channel Modes
        2. 7.3.14.2 Daisy Chain
        3. 7.3.14.3 Diagnostic Flags
        4. 7.3.14.4 ADC Output Data Randomizer
        5. 7.3.14.5 Test Patterns for Data Interface
        6. 7.3.14.6 Digital Output Drive Strength Control
        7. 7.3.14.7 Digital Output Delay Adjustment
    4. 7.4 Device Functional Modes
      1. 7.4.1 Reset
      2. 7.4.2 Normal Operation
      3. 7.4.3 Standby Mode
    5. 7.5 Programming
      1. 7.5.1 Register Write Operation
      2. 7.5.2 Register Read Operation
      3. 7.5.3 Initialization Example - Single Lane Mode on SDOUT
  9. 8 Register Maps
    1. 8.1 ADS93xx Common Registers
    2. 8.2 AIN1 - AIN8 Channel Registers
    3. 8.3 AIN9 - AIN16 Channel Registers
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 16-Channel, Data Acquisition System (DAQ) for Power Automation
        1. 9.2.1.1 Application Curve
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
        1. 9.4.1.1 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Mechanical Data

7.3.14.5 Test Patterns for Data Interface

The test pattern is a 16-bit value that replaces the ADC output data MSB with predefined digital data. Enable the test patterns by configuring the TP_CFG register (0x2E) in theAIN1 - AIN8 Channel and AIN9 - AIN16 Channel register banks.

Table 7-14 lists the test patterns supported by the ADS93x4.

Table 7-14 Test Pattern Configurations
TP_EN TP_MODE[2:0] TP_DIS_IDX TP_UPD_MODE ADC OUTPUT RESULT (See the notes)
0 X X 0 ADC conversion result ADC conversion result
1 0 1 0 Fixed pattern AIN1 = TP_AIN1, AIN2 = TP_AIN2, .., AIN15 = TP_15, AIN16 = TP_16.
1 0 0 0 Fixed pattern AIN1 = 0x0000+TP_AIN1, AIN2 = 0x1000+TP_AIN2, .. , AIN15 = 0xE000+TP_15,AIN16 = 0xF000+TP_16.
1 1 1 0 Ramp pattern Ramp pattern increments at channel frame boundary (see the Figure 7-37 and Figure 7-39).
1 2 1 1 Ramp pattern Ramp pattern increment at sample frame boundary. AIN1=AIN2=AIN3.. =AIN8;
AIN9=AIN10=AIN11.. =AIN16; See the Figure 7-38 and Figure 7-40
Note:
  1. Configure the test patterns for two separate channel groups AIN1_8 and AIN9_16.
  2. When using 24-bit ADC output, last 8-bits are zeros.
  3. TP_AIN1 and TP_AIN16 control the ramp step for AIN1 to AIN8 and AIN9 to AIN16 respectively.
  4. Ramp step is TP_AIN1 +1 and TP_AIN16 +1 for AIN1 to AIN8 and AIN9 to AIN16 respectively.
ADS9324 Digital Ramp Test Pattern, Increment at Channel Frame Boundary (TP_UPD_MODE =0)Figure 7-37 Digital Ramp Test Pattern, Increment at Channel Frame Boundary (TP_UPD_MODE =0)
ADS9324 Ramp Test Pattern Example, Step = 8 (TP_AIN1 =7, TP_UPD_MODE =0)Figure 7-39 Ramp Test Pattern Example, Step = 8 (TP_AIN1 =7, TP_UPD_MODE =0)
ADS9324 Digital Ramp Test Pattern, Increment at Sample Frame Boundary (TP_UPD_MODE =1)Figure 7-38 Digital Ramp Test Pattern, Increment at Sample Frame Boundary (TP_UPD_MODE =1)
ADS9324 Ramp Test Pattern Example, Step = 8 (TP_AIN1 =7, TP_UPD_MODE =1)Figure 7-40 Ramp Test Pattern Example, Step = 8 (TP_AIN1 =7, TP_UPD_MODE =1)