SBASB22 December   2025 ADS9324

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Switching Characteristics
    8. 5.8 Timing Diagrams
  7. 6 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Analog Inputs
      2. 7.3.2  Input Clamp Protection Circuit
      3. 7.3.3  Analog Input Impedance
      4. 7.3.4  Programmable Gain Amplifier (PGA)
      5. 7.3.5  ADC Transfer Function
      6. 7.3.6  Reference
      7. 7.3.7  Open Wire Safe Mode
      8. 7.3.8  System Offset Calibration
      9. 7.3.9  System Gain Calibration
      10. 7.3.10 ADC Gain and Offset Error Calibration
      11. 7.3.11 Digital Filter
        1. 7.3.11.1 System Phase Calibration
        2. 7.3.11.2 Block Average Filter
        3. 7.3.11.3 Moving Average Filter
        4. 7.3.11.4 Low-Pass FIR Filter
      12. 7.3.12 Digital Window Comparator
      13. 7.3.13 Alarm Modes
      14. 7.3.14 Data Interface
        1. 7.3.14.1 ADC Channel Modes
        2. 7.3.14.2 Daisy Chain
        3. 7.3.14.3 Diagnostic Flags
        4. 7.3.14.4 ADC Output Data Randomizer
        5. 7.3.14.5 Test Patterns for Data Interface
        6. 7.3.14.6 Digital Output Drive Strength Control
        7. 7.3.14.7 Digital Output Delay Adjustment
    4. 7.4 Device Functional Modes
      1. 7.4.1 Reset
      2. 7.4.2 Normal Operation
      3. 7.4.3 Standby Mode
    5. 7.5 Programming
      1. 7.5.1 Register Write Operation
      2. 7.5.2 Register Read Operation
      3. 7.5.3 Initialization Example - Single Lane Mode on SDOUT
  9. 8 Register Maps
    1. 8.1 ADS93xx Common Registers
    2. 8.2 AIN1 - AIN8 Channel Registers
    3. 8.3 AIN9 - AIN16 Channel Registers
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 16-Channel, Data Acquisition System (DAQ) for Power Automation
        1. 9.2.1.1 Application Curve
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
        1. 9.4.1.1 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Mechanical Data

7.3.12 Digital Window Comparator

The ADS93x4 has an 8-bit digital window comparator (DWC) for each input channel. Figure 7-24 shows the block diagram of the digital comparator. The low-side threshold, high-side threshold, and hysteresis parameters are independently programmable for each input channel. By default, hysteresis is 0, the high threshold is 127 (0x7F), and the low threshold is -128 (0x80). The DWC sets the DWC output to HIGH when the ADC output exceeds the high threshold or goes below the low threshold. The hysteresis field is an 8-bit field, and users can set the field to be from 0 to 255. The DWC also includes a glitch reject filter inside each DWC. The glitch reject filter is a 4-bit counter that counts if the ADC data exceeds the high or low thresholds for a consecutive number of ADC conversion clocks before asserting HIGH at the low and high comparator output. The glitch reject filter and user DWC reset bit are common for AIN1 to AIN8, and AIN9 to AIN16 channel groups. A rising edge transition on the DWC_RSTx user bit resets the digital window comparator flags.

ADS9324 Digital Window Comparator Functional Block Diagram Figure 7-24 Digital Window Comparator Functional Block Diagram

To enable the digital window comparator, set the DWC_EN bit in the DWC_CFG registers in AIN1 - AIN8 Channel and AIN9 - AIN16 Channel regbank. High and low flag status of each window comparator can be read using DWC_FLAG_AIN1_8 and DWC_FLAG_AIN8_16 registers. By default, the glitch reject counter is set to 0000'b. In case of an event, the glitch reject filter counts the number of high or low threshold violations before setting HIGH and LOW flags. The DWC also provides interrupt output, DWC_ALERT_INT, which is OR'ed output of high and low comparators. DWC_ALERT_INT signal goes to ALARM pin, and can be provided as output on the DRDY/ALARM pin by configuring the ALARM pin (see the Section 7.3.13). The DWC_ALERT_INT can be programmed as a level based (ALRM_TYP = 0b) or a pulse output (ALRM_TYP = 1b). High or low alert interrupt signals can be selected by setting high or low thresholds to maximum or minimum values. The behavior of the digital comparator is illustrated in Figure 7-25 .

  • If only HIGH_FLAG or HIGH_ALERT signals are required, program the LOW_TH_AINn to -128 (negative maximum value).
  • If only LOW_FLAG or LOW_ALERT signals are needed, program the HIGH_TH_AINn to 127 (positive maximum value).

ADS9324 Digital Window Comparator Behavior Figure 7-25 Digital Window Comparator Behavior