SBASB22 December   2025 ADS9324

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Switching Characteristics
    8. 5.8 Timing Diagrams
  7. 6 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Analog Inputs
      2. 7.3.2  Input Clamp Protection Circuit
      3. 7.3.3  Analog Input Impedance
      4. 7.3.4  Programmable Gain Amplifier (PGA)
      5. 7.3.5  ADC Transfer Function
      6. 7.3.6  Reference
      7. 7.3.7  Open Wire Safe Mode
      8. 7.3.8  System Offset Calibration
      9. 7.3.9  System Gain Calibration
      10. 7.3.10 ADC Gain and Offset Error Calibration
      11. 7.3.11 Digital Filter
        1. 7.3.11.1 System Phase Calibration
        2. 7.3.11.2 Block Average Filter
        3. 7.3.11.3 Moving Average Filter
        4. 7.3.11.4 Low-Pass FIR Filter
      12. 7.3.12 Digital Window Comparator
      13. 7.3.13 Alarm Modes
      14. 7.3.14 Data Interface
        1. 7.3.14.1 ADC Channel Modes
        2. 7.3.14.2 Daisy Chain
        3. 7.3.14.3 Diagnostic Flags
        4. 7.3.14.4 ADC Output Data Randomizer
        5. 7.3.14.5 Test Patterns for Data Interface
        6. 7.3.14.6 Digital Output Drive Strength Control
        7. 7.3.14.7 Digital Output Delay Adjustment
    4. 7.4 Device Functional Modes
      1. 7.4.1 Reset
      2. 7.4.2 Normal Operation
      3. 7.4.3 Standby Mode
    5. 7.5 Programming
      1. 7.5.1 Register Write Operation
      2. 7.5.2 Register Read Operation
      3. 7.5.3 Initialization Example - Single Lane Mode on SDOUT
  9. 8 Register Maps
    1. 8.1 ADS93xx Common Registers
    2. 8.2 AIN1 - AIN8 Channel Registers
    3. 8.3 AIN9 - AIN16 Channel Registers
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 16-Channel, Data Acquisition System (DAQ) for Power Automation
        1. 9.2.1.1 Application Curve
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
        1. 9.4.1.1 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Mechanical Data

7.3.10 ADC Gain and Offset Error Calibration

The ADS93x4 includes a ADC calibration module (ADC_CAL) for every ADC channel. Any change in ADC gain and offset error due to changes in the ambient temperature can be calibrated using this calibration. When ADC_CAL is running, the external input signal is disconnected from the ADC, and the ADC waits for TWAIT time to calibrate the gain and offset error of the all channels (see the Figure 7-10). The ADC calibration module doesn't affect the signals at the AINnP and AINnM input pins. After TWAIT time (see the Table 7-7), the ADC is automatically reconnected to the AINnP and AINnM input pins. ADC_CAL is an optional feature and requires user triggering to initiate operation. If the user is performing system-level offset and gain calibration, either using the on-chip system gain and offset error feature or in the host, ADC_CAL is not required. The ADC_CAL feature is useful when the user is not performing any system level calibration, and requires low ADC offset and gain error at power-up.

ADS9324 ADC_CAL Functional Block Diagram Figure 7-10 ADC_CAL Functional Block Diagram
Table 7-7 ADC Calibration Time (TWAIT)
ADC_CAL MODE INT_TRIG_MODE TWAIT Time
Free running CONVST 0b 100,000   x   t CONVST
Single-shot 1b 125ms

Figure 7-11 and Figure 7-12 show ADC output code when input shorted to ground before and after ADC calibration is performed. Channel-channel to offset error gets reduced from 40LSB16 to 15LSB16, and offset error is reduced from ±30LSB16 to ±8LSB16 after calibration is performed.

ADS9324 Offset Error before ADC Calibration
RANGE = ±5V, low-bandwidth, single-ended, VIN = 0V,
channel-to-channel offfset mismatch = 40LSB16,
offset error = ±30LSB16
Figure 7-11 Offset Error before ADC Calibration
ADS9324 Offset Error after ADC Calibration
RANGE = ±5V, low-bandwidth, single-ended, VIN = 0V,
channel-to-channel offfset mismatch = 15LSB16,
offset error = ±8LSB16
Figure 7-12 Offset Error after ADC Calibration

ADC calibration block is configured using ADC_CAL register in the ADS93x4 Common register bank. Before running ADC calibration module, enable common mode error correction feature if required and disable digital filters. By default digital filters are disabled. ADC calibration module requires user to provide analog input configuration. Depending on the single ended or differential analog mode, update SE_DIFF_MODE_AIN9_16 and SE_DIFF_MODE_AIN1_8 bit fields in the ADC_CAL register. See below for steps required to run the ADC gain and offset error calibration module.

ADC calibration (single-shot mode):

  1. Set the INT_TRIG_MODE to 1b.
  2. The ADC calibration module supports three calibration modes, offset calibration, gain calibration, and offset and gain calibration. Update ADC_CAL_MODE bit field to 01b, 10b and 11b for offset only, gain only and, offset and gain calibration. Writing 00b on the ADC_CAL_MODE disables the automatic calibration block and calibration value applied to the ADC data output. Ensure this field is set to 01b, 10b or 11b if the ADC calibration feature is used.
  3. Write 0b to 1b for a rising edge transition on the ADC_CAL_TRIG bit.
  4. Wait for 10µs.
  5. Write ADC_CAL_TRIG bit to 0b.
  6. Send a single clock pulse to the device. At least one falling edge must be provided. If the clock idle state was low, the device requires a low-high pulse sequence. End state of the CONVST must be high.
  7. Wait for 125ms. Alternatively, the user can read the CALIB_BUSY flag status to determine when calibration is complete.
  8. User can now operate the ADC in normal operation.

ADC calibration with continuous CONVST signal: Use the below programming sequence to configure the ADC_CAL block if INT_TRIG_MODE is programmed to 0b.

  1. Ensure a free running CONVST clock is provided to the ADC.
  2. The ADC calibration module supports three calibration modes, offset only calibration, gain only calibration, and offset and gain calibration. Update ADC_CAL_MODE bit field to 01b, 10b and 11b for offset only, gain only and, offset and gain calibration. Writing 00b on the ADC_CAL_MODE disables the automatic calibration block and calibration value applied to the ADC data output. Ensure this field is set to 01b, 10b or 11b if the ADC calibration feature is used.
  3. Write 0b to 1b for a rising edge transition on the ADC_CAL_TRIG bit.
  4. Ensure at least one tCONVST delay time.
  5. Write ADC_CAL_TRIG bit to 0b.
  6. Wait for 100,000 CONVST clock cycles. For 1MHz CONVST, the wait time required is 100ms.
  7. User can now operate the ADC in normal operation.