SBASB22 December   2025 ADS9324

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Switching Characteristics
    8. 5.8 Timing Diagrams
  7. 6 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Analog Inputs
      2. 7.3.2  Input Clamp Protection Circuit
      3. 7.3.3  Analog Input Impedance
      4. 7.3.4  Programmable Gain Amplifier (PGA)
      5. 7.3.5  ADC Transfer Function
      6. 7.3.6  Reference
      7. 7.3.7  Open Wire Safe Mode
      8. 7.3.8  System Offset Calibration
      9. 7.3.9  System Gain Calibration
      10. 7.3.10 ADC Gain and Offset Error Calibration
      11. 7.3.11 Digital Filter
        1. 7.3.11.1 System Phase Calibration
        2. 7.3.11.2 Block Average Filter
        3. 7.3.11.3 Moving Average Filter
        4. 7.3.11.4 Low-Pass FIR Filter
      12. 7.3.12 Digital Window Comparator
      13. 7.3.13 Alarm Modes
      14. 7.3.14 Data Interface
        1. 7.3.14.1 ADC Channel Modes
        2. 7.3.14.2 Daisy Chain
        3. 7.3.14.3 Diagnostic Flags
        4. 7.3.14.4 ADC Output Data Randomizer
        5. 7.3.14.5 Test Patterns for Data Interface
        6. 7.3.14.6 Digital Output Drive Strength Control
        7. 7.3.14.7 Digital Output Delay Adjustment
    4. 7.4 Device Functional Modes
      1. 7.4.1 Reset
      2. 7.4.2 Normal Operation
      3. 7.4.3 Standby Mode
    5. 7.5 Programming
      1. 7.5.1 Register Write Operation
      2. 7.5.2 Register Read Operation
      3. 7.5.3 Initialization Example - Single Lane Mode on SDOUT
  9. 8 Register Maps
    1. 8.1 ADS93xx Common Registers
    2. 8.2 AIN1 - AIN8 Channel Registers
    3. 8.3 AIN9 - AIN16 Channel Registers
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 16-Channel, Data Acquisition System (DAQ) for Power Automation
        1. 9.2.1.1 Application Curve
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
        1. 9.4.1.1 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Mechanical Data

7.1 Overview

The ADS9324 is a 16-bit simultaneous sampling data acquisition (DAQ) system with sixteen analog input channels configurable as either single-ended or differential. Each analog input channel consists of an input clamp protection circuit and a programmable gain amplifier (PGA) with user-selectable bandwidth options. The input signals are digitized with a 16-bit analog-to-digital converter (ADC), based on the successive approximation register (SAR) architecture. This overall system achieves a maximum throughput of 1MSPS per channel for all channels. The device has a 4.096V internal precision reference with a buffer to drive the ADC.

The device operates from 5V and 1.8V analog supplies and accommodates true bipolar input signals. The device offers a constant 1MΩ resistive input impedance irrespective of the sampling frequency or the selected input range. The ADS9324 offers a simplified end design without requiring external amplifiers, high-voltage bipolar supplies, and complicated driver circuits. The device supports both differential and single-ended inputs, allowing it to be used with various sensor outputs. For single-ended inputs, it includes an open-wire safe mode, which results in a near-zero ADC output code if a sensor is suddenly disconnected from the ADC inputs.

Each channel on the ADS9324 contains optional digital filters to improve noise performance of the ADC. The digital filter supports block average, moving average and low pass FIR modes. The ADS9324 also contains offset, gain and phase calibration features that can be programmed to automatically adjust the ADC output for measured offset, gain and phase errors. The device includes a ADC calibration (ADC_CAL) module to calibrate the ADC errors and reduces the channel to channel offset and gain mistmatch. The ADC_CAL feature is useful when the user is not performing any system-level calibration, and requires low ADC offset and gain error at power-up.

The ADS9324 includes a flexible digital interface allowing it to be used with a variety of host controllers. Users can configure the serial interface to read the ADC output on 1-lane, 2-lane, 4-lane, and 8-lane. The device also has flexibility to operate the ADC as 2-CH, 4-CH, 8-CH and 16-CH simultaneous sampling ADC. An ADC output randomizer feature is also provided to minimize interference between data transmission and analog performance of the ADC when the PCB layout does not minimize ground bounce.