SBASB22 December   2025 ADS9324

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Switching Characteristics
    8. 5.8 Timing Diagrams
  7. 6 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Analog Inputs
      2. 7.3.2  Input Clamp Protection Circuit
      3. 7.3.3  Analog Input Impedance
      4. 7.3.4  Programmable Gain Amplifier (PGA)
      5. 7.3.5  ADC Transfer Function
      6. 7.3.6  Reference
      7. 7.3.7  Open Wire Safe Mode
      8. 7.3.8  System Offset Calibration
      9. 7.3.9  System Gain Calibration
      10. 7.3.10 ADC Gain and Offset Error Calibration
      11. 7.3.11 Digital Filter
        1. 7.3.11.1 System Phase Calibration
        2. 7.3.11.2 Block Average Filter
        3. 7.3.11.3 Moving Average Filter
        4. 7.3.11.4 Low-Pass FIR Filter
      12. 7.3.12 Digital Window Comparator
      13. 7.3.13 Alarm Modes
      14. 7.3.14 Data Interface
        1. 7.3.14.1 ADC Channel Modes
        2. 7.3.14.2 Daisy Chain
        3. 7.3.14.3 Diagnostic Flags
        4. 7.3.14.4 ADC Output Data Randomizer
        5. 7.3.14.5 Test Patterns for Data Interface
        6. 7.3.14.6 Digital Output Drive Strength Control
        7. 7.3.14.7 Digital Output Delay Adjustment
    4. 7.4 Device Functional Modes
      1. 7.4.1 Reset
      2. 7.4.2 Normal Operation
      3. 7.4.3 Standby Mode
    5. 7.5 Programming
      1. 7.5.1 Register Write Operation
      2. 7.5.2 Register Read Operation
      3. 7.5.3 Initialization Example - Single Lane Mode on SDOUT
  9. 8 Register Maps
    1. 8.1 ADS93xx Common Registers
    2. 8.2 AIN1 - AIN8 Channel Registers
    3. 8.3 AIN9 - AIN16 Channel Registers
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 16-Channel, Data Acquisition System (DAQ) for Power Automation
        1. 9.2.1.1 Application Curve
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
        1. 9.4.1.1 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Mechanical Data

5.7 Switching Characteristics

at AVDD_5V = 4.75V to 5.25V, AVDD_1V8 = 1.7V to 1.9V, IOVDD = 1.7 to 1.9V, VREF = 4.096V (internal or external), and maximum throughput (unless otherwise noted); minimum and maximum values at TA = –40°C to +125°C; typical values at TA = 25°C
PARAMETER TEST CONDITIONS MIN MAX UNIT
RESET
tPU Power-up time for device 1-μF capacitor on REFCAP pin 30 ms
SERIAL INTERFACE
td_CSDO Delay time: CS falling edge to data valid on
SDOUT and D[7:0]		 16 ns
tdz_CSDO Delay time: CS rising edge to SDOUT and and D[7:0] going Hi-Z 7.5 ns
tvt_CKDO Valid time: SCLK launch edge to previous
data valid on SDOUT and D[7:0]		 7.6 ns
td_CKDO Delay time: SCLK launch edge to
corresponding data valid on SDOUT and D[7:0]		 17 ns
DRDY AND ALARM
tCYC ADC cycle time period 1 / fCONVST µs
tCONV ADC conversion time: conversion data is available for read No oversampling 1.25 µs
Oversampling ratio N (N-1)*tCYC + 1.25 µs
td_CVDRDY_hi Data ready time, time delay between CONVST falling edge to DRDY rising edge tCONV µs
td_CVDRDY_lo Time delay between CONVST falling edge to DRDY falling edge 350 ns
td_ALARM Time delay between CONVST falling edge to new ALARM valid tCONV µs