SBOSAJ7A October   2025  – December 2025 TMP4719

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 I2C Interface Timing
    7. 6.7 Timing Diagrams
    8. 6.8 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Device Initialization and Default Temperature Conversion
      2. 7.3.2 Series Resistance Cancellation
      3. 7.3.3 ALERT and T_CRIT Output
      4. 7.3.4 1.2V Logic Compatible Inputs
      5. 7.3.5 Digital Filter
      6. 7.3.6 One-Shot Conversions
    4. 7.4 Device Functional Modes
      1. 7.4.1 Interrupt and Comparator Mode
        1. 7.4.1.1 Interrupt Mode
        2. 7.4.1.2 Comparator Mode
        3. 7.4.1.3 T_CRIT Output
      2. 7.4.2 Shutdown Mode
      3. 7.4.3 Continuous Conversion Mode
    5. 7.5 Programming
      1. 7.5.1 Temperature Data Format
      2. 7.5.2 I2C and SMBus Interface
      3. 7.5.3 Serial Bus Address
      4. 7.5.4 Bus Transactions
        1. 7.5.4.1 Writes
        2. 7.5.4.2 Reads
      5. 7.5.5 SMBus Alert Mode
  9. 8 Register Map
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curve
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

7.5.5 SMBus Alert Mode

When the Alert Mode Setting bit in the Configuration Register is set to 0, the Interrupt/SMBus Alert mode is enabled. In this mode, the ALERT pin is asserted at the end of a conversion cycle if the measured temperature exceeds a High Alert Limit or goes below a Low Alert Limit defined in the limit registers. In this mode, the TMP4719 sets the ALERT mask bit of the Configuration Register during a read of the Status Register if any flag in the Status Register, except the ADC_Busy flag and Remote Diode Fault flag, is set. This prevents the ALERT pin from triggering until the controller resets the ALERT mask bit (write 0 to the Alert_MASK bit).

The ALERT High Status flag is set at the end of a conversion cycle when the measured temperature exceeds a High Alert Limit register limit. There are separate High Limit values and status register flags for the remote and local temperature measurements. The High Limit Status register flags are only set to the respective temperature measurements.

The ALERT Low Status flag is set at the end of a conversion cycle when the measured temperature is below a Low Alert Limit register limit. There are separate Low Limit values and status register flags for the remote and local temperature measurements. The Low Limit Status register flags are only set to the respective temperature measurements.

The Status Register limit flags are cleared after a read command of the Status Register from the controller and are set again at the end of a temperature conversion cycle if the measured temperature is outside the set limits.

When the ALERT pin is connected to the SMBus alert line, there can be multiple devices on the same output. For the controller to resolve which target is generating an alert, the controller can send an SMBus ALERT Response Address (ARA) command. If the TMP4719 is generating an alert, and an ARA command is sent, the TMP4719 sets the ALERT MASK bit in the Configuration register and sends the target address to the controller. An ARA command does not clear any Status register flags. A read command of the Status Register from the controller is required to clear the Status Register limit flags.

Figure 7-15 shows the behavior of the ALERT pin and flags while in SMBus Alert mode.

TMP4719 Alert SMBus Mode Timing DiagramFigure 7-15 Alert SMBus Mode Timing Diagram