SCES983 October   2025 TXB0604

ADVANCE INFORMATION  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Electrical Characteristics
    5. 5.5 Switching Characteristics, VCCA = 0.9V
    6. 5.6 Switching Characteristics, VCCA = 1.2V
    7. 5.7 Switching Characteristics, VCCA = 1.5V ± 0.1V
    8. 5.8 Switching Characteristics, VCCA = 1.8V ± 0.15V
    9. 5.9 Switching Characteristics: Tsk, TMAX (-40°C to 125°C) 
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Architecture
      2. 7.3.2 Input Driver Requirements
      3. 7.3.3 Output Load Considerations
      4. 7.3.4 Enable and Disable
      5. 7.3.5 Pullup or Pulldown Resistors on I/O Lines
      6. 7.3.6 Dummy Cycles
    4. 7.4 Device Functional Modes
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
  10. 9 Power Supply Recommendations
  11. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  12. 11Device and Documentation Support
    1. 11.1 Receiving Notification of Documentation Updates
    2. 11.2 Support Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  13. 12Revision History
  14. 13Mechanical, Packaging, and Orderable Information

7.3.6 Dummy Cycles

When TXB0604 is used in Quad-SPI (QSPI) interfaces between a microcontroller and serial flash memory, the direction of the data flow can change dynamically between the controller and the memory device. Given the TXB0604 features automatic direction sensing, a minimum turn-around time of 40ns is required for the device to transition from one direction to the other. This is shown under the Switching Characteristics table as tDCW - Direction Change Wait Time.

The ensure proper bus timing, the QSPI controller must insert sufficient dummy clock cycles after the command and address phase before data is sampled from the flash memory. The total dummy period must be greater or equal to the TXB0604 turn-around time of 40ns.

As an example, at a QSPI clock frequency of 104MHz:

Equation 1. 1 / 104 M H z   =   9 . 6 n s
Equation 2. 40 n s / 9 . 6 n s   =   4 . 16 n s   →   5   d u m m y   c y c l e s

Many flash devices, such as the ISSI IS25LQ040B, specificy 8 dummy cycles at 104MHz frequency, which satisfies the TXB0604 requirement and provides additional margin.