SLAAED9 November 2023 TAA5412-Q1 , TAC5311-Q1 , TAC5312-Q1 , TAC5411-Q1 , TAC5412-Q1
This register is the live Interrupt status register for channel level diagnostic summary.
Bit | Field | Type(1) | Reset | Description |
---|---|---|---|---|
7 | STS_CHx_LIVE | R | 0b | Status of Input CH1_LIVE 0b = No faults occurred in input channel 1 1b = Fault or faults have occurred in input channel 1 |
6 | STS_CHx_LIVE | R | 0b | Status of Input CH2_LIVE 0b = No faults occurred in input channel 2 1b = Fault or faults have occurred in input channel 2 |
5 | STS_CHx_LIVE | R | 0b | Status of Output CH1_LIVE 0b = No faults occurred in output channel 1 1b = Fault or faults have occurred in output channel 1 |
4 | STS_CHx_LIVE | R | 0b | Status of Output CH2_LIVE 0b = No faults occurred in output channel 2 1b = Fault or faults have occurred in output channel 2 |
3 | STS_CHx_LIVE | R | 0b | Status on fault due to "Short to VBAT_IN fault detected when VBAT_IN is less than MICBIAS" 0b = Short to VBAT_IN fault when VBAT_IN is less than MICBIAS did NOT occur in any channel 1b = Short to VBAT_IN fault when VBAT_IN is less than MICBIAS has occurred in at least one channel |
2 | RESERVED | R | 0b | Reserved bit; Write only reset value |
1 | RESERVED | R | 0b | Reserved bit; Write only reset value |
0 | RESERVED | R | 0b | Reserved bit; Write only reset value |
The respective CH_LIVE registers P0_R63 and P0_R64 contain the details of exactly which faults occurred on a given channel. Section 6.1.2 shows CH1_LIVE register for reference.