Preceding the output pins is an amplifier operating at AVDD that creates a midpoint voltage to serve as a reference point for the analog input signal. This midpoint voltage, shown as V_ICM (which stands for "internal common-mode") in Figure 3-8, is referred to as the virtual ground. A fault is triggered if there is a short at OUTx that brings the virtual ground to unintended high voltages. Furthermore, a fault can be triggered under the following conditions:

• If the analog input signal common mode is higher than 100 mV, thus breaking the limitation of R_BYP and bringing the virtual ground to unintended high voltages. This is only applicable when the device output configuration is fully-differential.
• If the device is configured to have a 6-db or 12-dB gain in bypass and the input signal is greater than -6-dB or -12-dB respectively. This is applicable to single-ended or fully-differential output configurations.
• If the analog input level exceeds the full scale input signal range for the respective input configuration.

Correct configuration of the output registers for channel 1 (P0_R100-R102) and channel 2 (P0_R107-R109) is essential to prevent unintended virtual ground fault detection. In the event a virtual ground fault is detected, the user must check the output configuration registers and verify compliance with the input signal and voltages.

In addition, the DAC output stage is shown in Figure 3-8 and if the voltage measured at OUTx exceeds the design limits of the device, this fault triggers. The user has the ability to program the device in DAC_FLT_CFG (P0_R67) to power down the playback path of the DAC upon fault detection.

Figure 3-8 Virtual Ground Output Configuration