SLAAEQ4 July   2025 MSPM0G1106 , MSPM0G1107 , MSPM0G1506 , MSPM0G1507 , MSPM0G1518 , MSPM0G1519 , MSPM0G3106 , MSPM0G3106-Q1 , MSPM0G3107 , MSPM0G3107-Q1 , MSPM0G3506 , MSPM0G3506-Q1 , MSPM0G3507 , MSPM0G3507-Q1 , MSPM0G3518 , MSPM0G3518-Q1 , MSPM0G3519 , MSPM0G3519-Q1

 

  1.   1
  2.   Trademarks
  3. 1Introduction
    1. 1.1 Features Supported
    2. 1.2 CAN Frame Format
    3. 1.3 SPI Message Frame Format
  4. 2Implementation
    1. 2.1 SPI Message Format
      1. 2.1.1 SPI Commands
      2. 2.1.2 Instruction Set
    2. 2.2 Timeout Feature
    3. 2.3 Error Indication
    4. 2.4 Busy Status Indication
    5. 2.5 Message RAM Configuration
    6. 2.6 Test Environment
  5. 3References

2.1 SPI Message Format

A sample SPI message frame is shown in Figure 2-1. Each message frame is split into:

  • Instruction: lower 8 bits of 16-bit frame is used.
  • Address offset: 16 bits (only lower 16 bits of address needs to be sent). Refer MSPM0G3507 Technical Reference Manual for register description and address.
  • Data mask: 32 bits – two 16-bit frames with LSB first.
  • Data: 32 bits – two 16-bit frames with LSB first.
MSPM0G3507 SPI Message Format Figure 2-1 SPI Message Format