SLAAET4 April   2025 MSPM0G3506 , MSPM0G3507 , MSPM0G3518 , MSPM0G3519

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
    1. 1.1 MCAN Features
  5. 2Sysconfig Configuration for MCAN Module
    1. 2.1 MCAN Clock Frequency
    2. 2.2 MCAN Basic Configuration
      1. 2.2.1 Transmitter Delay Compensation (TDC)
      2. 2.2.2 Bit Timing Parameters
      3. 2.2.3 Message RAM Configuration
        1. 2.2.3.1 Standard and Extended ID Filter Configuration
          1. 2.2.3.1.1 How to Add More Filters
        2. 2.2.3.2 TX MSG RAM
        3. 2.2.3.3 RX MSG RAM
    3. 2.3 Advanced Configuration
    4. 2.4 Retention Configuration
    5. 2.5 Interrupts
    6. 2.6 Pin Configuration and PinMux
  6. 3Demo Project Descriptions
    1. 3.1 TX Buffer Mode
    2. 3.2 TX FIFO Mode
    3. 3.3 RX Buffer Mode
    4. 3.4 RX FIFO Mode
  7. 4Debug and Design Tips to Resolve/Avoid CAN Communication Issues
    1. 4.1 Minimum Number of Nodes Required
    2. 4.2 Why a Transceiver is Needed
    3. 4.3 Bus Off Status
    4. 4.4 Using MCAN in Low Power Mode
    5. 4.5 Debug Checklist
      1. 4.5.1 Programming Issues
      2. 4.5.2 Physical Layer Issues
      3. 4.5.3 Hardware Debug Tips
  8. 5Summary
  9. 6References

3.4 RX FIFO Mode

The RX is configured as FIFO mode in the current demo projects in SDK. The section below introduces the structure of DL_MCAN_RxFIFOStatus, which is commonly used in RX FIFO mode. TI recommends for the users to check this structure when pulling the message from RX FIFO. 

/**
 *  @brief  Structure for MCAN Rx FIFO Status.
 */
typedef struct {
    /*! Rx FIFO number
     *   One of @ref DL_MCAN_RX_FIFO_NUM
     */
    uint32_t num;
    /*! Rx FIFO Fill Level */
    uint32_t fillLvl;
    /*! Rx FIFO Get Index */
    uint32_t getIdx;
    /*! Rx FIFO Put Index */
    uint32_t putIdx;
    /*! Rx FIFO Full
     *   0 = Rx FIFO not full
     *   1 = Rx FIFO full
     */
    uint32_t fifoFull;
    /*! Rx FIFO Message Lost */
    uint32_t msgLost;
} DL_MCAN_RxFIFOStatus;
  • The num indicates the Rx FIFO instance number of the current operation. MCAN can support multiple Rx FIFOs (such as Rx FIFO 0 and Rx FIFO 1), and the specific instance must be specified. For example, the DL_MCAN_RX_FIFO_NUM enumeration contains DL_MCAN_RX_FIFO_0 and DL_MCAN_RX_FIFO_1.
  • The fillLvl indicates the number of valid messages currently stored in the Rx FIFO. For example, when fillLvl is 5, this means there are 5 unread messages in the FIFO. When fillLvl reaches the depth of the Rx FIFO (such as 6 messages), the fifoFull field is set to 1, indicating that the FIFO is full.
  • The getIdx points to the next message to be read. The CPU reads the messages in the FIFO sequentially by incrementing getIdx. When the Rx FIFO is full and in overwrite mode, new messages overwrite the oldest messages. At this time, user starts reading from getIdx + 1 to avoid reading old data that is being overwritten.
  • The putIdx points to the next writable message location. When a new message is received, the message is written to the location pointed to by putIdx, and then putIdx is incremented.
  • The fifoFull indicates the Rx FIFO is full or not. When Rx FIFO is full, try the following options:
    • Blocking mode: new messages are discarded and the msgLost count is triggered.
    • Overwrite mode: the new message overwrites the oldest message, putIdx and getIdx are incremented at the same time.
  • The msgLost counts the number of messages discarded due to Rx FIFO full. This is triggered in the following situations:
    • Blocking mode: when the Rx FIFO is full, a new message is received and the message is rejected and discarded.
    • Overwrite mode: when overwriting old messages, the overwritten messages are counted as lost.