SLAAET4 April   2025 MSPM0G3506 , MSPM0G3507 , MSPM0G3518 , MSPM0G3519

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
    1. 1.1 MCAN Features
  5. 2Sysconfig Configuration for MCAN Module
    1. 2.1 MCAN Clock Frequency
    2. 2.2 MCAN Basic Configuration
      1. 2.2.1 Transmitter Delay Compensation (TDC)
      2. 2.2.2 Bit Timing Parameters
      3. 2.2.3 Message RAM Configuration
        1. 2.2.3.1 Standard and Extended ID Filter Configuration
          1. 2.2.3.1.1 How to Add More Filters
        2. 2.2.3.2 TX MSG RAM
        3. 2.2.3.3 RX MSG RAM
    3. 2.3 Advanced Configuration
    4. 2.4 Retention Configuration
    5. 2.5 Interrupts
    6. 2.6 Pin Configuration and PinMux
  6. 3Demo Project Descriptions
    1. 3.1 TX Buffer Mode
    2. 3.2 TX FIFO Mode
    3. 3.3 RX Buffer Mode
    4. 3.4 RX FIFO Mode
  7. 4Debug and Design Tips to Resolve/Avoid CAN Communication Issues
    1. 4.1 Minimum Number of Nodes Required
    2. 4.2 Why a Transceiver is Needed
    3. 4.3 Bus Off Status
    4. 4.4 Using MCAN in Low Power Mode
    5. 4.5 Debug Checklist
      1. 4.5.1 Programming Issues
      2. 4.5.2 Physical Layer Issues
      3. 4.5.3 Hardware Debug Tips
  8. 5Summary
  9. 6References

2.5 Interrupts

Figure 2-6 shows what parameters are included in Interrupts block.

Interrupts Figure 2-10 Interrupts

The MCAN module contains one event publisher (CPU_INT) that manages MCAN interrupt requests (IRQs) to the CPU subsystem by a static event route. Figure 2-11 shows the integration of the MCAN module in the device.

MCAN Integration Figure 2-11 MCAN Integration
  • MCAN Interrupts
    • Enable MCAN Interrupts: the MCAN core has two interrupt lines and 30 internal interrupt sources. Each source can be configured to drive one of the two interrupt lines. The MCAN core provides two interrupt requests Interrupt Line0 and Interrupt Line1.
    • Enable MCAN Line Interrupts: defines which interrupt lines are used in the application.
    • Interrupts To Trigger In Line0: defines which interrupt sources are assigned to Interrupt Line0.
    • Interrupts To Trigger In Line1: defines which interrupt sources are assigned to Interrupt Line1.
  • MSPM0 Interrupts
    • Enable MSPM0 MCAN Interrupts: the MCAN module provides different interrupt sources which can be configured to source a CPU interrupt event. In order of decreasing interrupt priority, the CPU interrupt events from the MCAN are configured here.