SLAAET4 April   2025 MSPM0G3506 , MSPM0G3507 , MSPM0G3518 , MSPM0G3519

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
    1. 1.1 MCAN Features
  5. 2Sysconfig Configuration for MCAN Module
    1. 2.1 MCAN Clock Frequency
    2. 2.2 MCAN Basic Configuration
      1. 2.2.1 Transmitter Delay Compensation (TDC)
      2. 2.2.2 Bit Timing Parameters
      3. 2.2.3 Message RAM Configuration
        1. 2.2.3.1 Standard and Extended ID Filter Configuration
          1. 2.2.3.1.1 How to Add More Filters
        2. 2.2.3.2 TX MSG RAM
        3. 2.2.3.3 RX MSG RAM
    3. 2.3 Advanced Configuration
    4. 2.4 Retention Configuration
    5. 2.5 Interrupts
    6. 2.6 Pin Configuration and PinMux
  6. 3Demo Project Descriptions
    1. 3.1 TX Buffer Mode
    2. 3.2 TX FIFO Mode
    3. 3.3 RX Buffer Mode
    4. 3.4 RX FIFO Mode
  7. 4Debug and Design Tips to Resolve/Avoid CAN Communication Issues
    1. 4.1 Minimum Number of Nodes Required
    2. 4.2 Why a Transceiver is Needed
    3. 4.3 Bus Off Status
    4. 4.4 Using MCAN in Low Power Mode
    5. 4.5 Debug Checklist
      1. 4.5.1 Programming Issues
      2. 4.5.2 Physical Layer Issues
      3. 4.5.3 Hardware Debug Tips
  8. 5Summary
  9. 6References

2.2.3.2 TX MSG RAM

Figure 2-6 shows what parameters are included in TX MSG RAM block.

TX MSG RAM Figure 2-6 TX MSG RAM

The Tx buffers section can be configured to hold dedicated Tx buffers as well as a Tx FIFO and Tx Queue. When the Tx buffers section is shared by dedicated Tx buffers and a Tx FIFO and Tx Queue, the dedicated Tx buffers start at the beginning of the Tx buffers section followed by the buffers assigned to the Tx FIFO or Tx Queue. Table 2-1 shows the differences between Tx buffer mode, Tx FIFO mode and Tx queue mode.

Table 2-1 Differences Between Tx Mode
Tx Mode Description
Tx buffer mode Dedicated Tx buffers are intended for message transmission under complete control of the host CPU.
Tx FIFO mode Tx FIFO allows transmission of messages with the same Message ID from different Tx buffers in the order these messages have been written to the Tx FIFO.
Tx queue mode The stored in the Tx Queue messages are transmitted starting with the highest priority message (lowest Message ID).
  • TX Buffers Start Address: the start address of Tx buffers in message RAM.
  • Number of Dedicated Transmit Buffers: defines how many elements are configured as dedicated Tx buffers.
  • No of TX FIFO Elements: defines how many elements are configured as Tx FIFO or Tx queue.
  • TX FIFO Operation Mode: defines the Tx FIFO mode or Tx queue mode.
  • TX Buffer Element Size: defines the Tx buffer data field size. In case the data length code DLC of a Tx Buffer element is configured to a value higher than the Tx Buffer data field size, the bytes not defined by the Tx Buffer are transmitted as 0xCC (padding bytes).
  • TX Event FIFO Start Address: the Tx Event FIFO stores information about transmitted messages. To support Tx event handling, the Message RAM has implemented a Tx Event FIFO section. By reading the Tx Event FIFO, the Host CPU gets this information in the order the messages were transmitted. After message transmission on the CAN bus, Message ID and Timestamp are stored in a Tx Event FIFO element. To link a Tx Event to a Tx Event FIFO element, the Message Marker from the transmitted Tx Buffer is copied into the Tx Event FIFO element.
  • TX Event FIFO Size: up to 32 Tx Event FIFO elements can be configured.
  • TX Event FIFO Watermark INT Level: defines Tx Event FIFO fill level threshold. The Tx Event FIFO watermark can be configured to avoid a Tx Event FIFO overflow.