SLAAET4 April   2025 MSPM0G3506 , MSPM0G3507 , MSPM0G3518 , MSPM0G3519

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
    1. 1.1 MCAN Features
  5. 2Sysconfig Configuration for MCAN Module
    1. 2.1 MCAN Clock Frequency
    2. 2.2 MCAN Basic Configuration
      1. 2.2.1 Transmitter Delay Compensation (TDC)
      2. 2.2.2 Bit Timing Parameters
      3. 2.2.3 Message RAM Configuration
        1. 2.2.3.1 Standard and Extended ID Filter Configuration
          1. 2.2.3.1.1 How to Add More Filters
        2. 2.2.3.2 TX MSG RAM
        3. 2.2.3.3 RX MSG RAM
    3. 2.3 Advanced Configuration
    4. 2.4 Retention Configuration
    5. 2.5 Interrupts
    6. 2.6 Pin Configuration and PinMux
  6. 3Demo Project Descriptions
    1. 3.1 TX Buffer Mode
    2. 3.2 TX FIFO Mode
    3. 3.3 RX Buffer Mode
    4. 3.4 RX FIFO Mode
  7. 4Debug and Design Tips to Resolve/Avoid CAN Communication Issues
    1. 4.1 Minimum Number of Nodes Required
    2. 4.2 Why a Transceiver is Needed
    3. 4.3 Bus Off Status
    4. 4.4 Using MCAN in Low Power Mode
    5. 4.5 Debug Checklist
      1. 4.5.1 Programming Issues
      2. 4.5.2 Physical Layer Issues
      3. 4.5.3 Hardware Debug Tips
  8. 5Summary
  9. 6References

2.2 MCAN Basic Configuration

Figure 2-1 shows what parameters are included in MCAN Basic Frequency block.

MCAN Basic Configuration Figure 2-2 MCAN Basic Configuration
  • Enable CAN FD Mode: where CAN flexible data mode needs to be enabled.
  • Enable Bit Rate Switching: by enabling this feature, MCAN sends data at higher rate instead of the arbitration rate. This function only works when CAN FD mode is enabled.
  • Enable Loopback Mode: transmitted messages become received messages. This allows users to monitor the CAN messages on the CAN_TX pin without a CAN transceiver.
  • Enable Transmit Pause: pauses for two CAN bit times before the next transmission. The transmit pause feature is intended for use in CAN networks where the CAN Message IDs are specific and cannot easily be changed. These Message IDs can have a higher priority than other defined Message IDs, while in a specific application, the relative priority is inverse. This allows for when one ECU sends a burst of CAN messages that causes CAN messages from another ECU to be delayed (paused).
  • Enable Edge Filtering: two consecutive dominant time quanta required to detect an edge for hard synchronization. Enabling this function is to make sure that nodes can accurately detect signal edges and perform hard synchronization under the condition of longer data bit times, thereby improving the stability and reliability of CAN bus communication.
  • Enable Protocol Exception Handling: detection of bits that are reserved for future protocol expansion.
  • Messages Will Only Be Sent Once: if automatic retransmission is disabled, then the MCAN module no longer retransmits when there is a transmission error, NACK, or the MCAN module loses arbitration.
  • Enable Wakeup Request: enables the MCAN module to wakeup on CAN RXD activity.
  • Enable Auto-Wakeup: enables the MCAN module to automatically clear the MCAN CCCR.INIT bit, fully waking the MCAN up on an enabled wakeup request. Issuing a clock stop request puts the MCAN module into powerdown mode (sleep mode). During transition from IDLE to ACTIVE, if the enable wakeup request and enable auto-wakeup functions are enabled, then a read-modify-write is issued to clear the MCAN_CCCR.INIT bit. The MCAN core resumes operation after the MCAN Core responds to the removal of the clock stop request with removing the clock stop acknowledge.
    Note: Note that after a clock stop request has been removed by the hardware, the first frame (wakeup frame) is not received. This is because after the clock stop is issued, there are no active clocks running into the IP. Therefore, after removing the clock stop request, the wakeup frame that enables the clock has to be retransmitted.
  • Enable Emulation or Debug Suspend: MCAN module can be suspended for emulation or debug.
  • Message RAM Watchdog Preload Value: the RAM Watchdog monitors the READY output of the Message RAM. A Message RAM access by the Generic Master Interface of the MCAN starts the Message RAM Watchdog Counter with the value configured. The counter is reloaded when the Message RAM signals successful completion by activating the READY output. In case there is no response from the Message RAM until the counter has counted down to zero, the counter stops and the interrupt flag MCAN_IR.WDI is set. The RAM Watchdog Counter is clocked by the host (system) clock.