SLOS970B January   2018  – January 2025 TPA6404-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Typical Characteristics
  7. 6 Parameter measurement Information
  8. 7 Detailed description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Differential Analog inputs
      2. 7.3.2 Gain Control and AC-Coupling
      3. 7.3.3 High-Frequency Pulse-Width Modulator (PWM)
      4. 7.3.4 Gate Drive
      5. 7.3.5 Power FETs
      6. 7.3.6 Load Diagnostics
        1. 7.3.6.1 DC Load Diagnostics
          1. 7.3.6.1.1 Automatic DC Load Diagnostics
          2. 7.3.6.1.2 I2C Controlled DC Load Diagnostics
        2. 7.3.6.2 Line Output Diagnostics
        3. 7.3.6.3 AC Load Diagnostics
          1. 7.3.6.3.1 Impedance Phase Reference Measurement
          2. 7.3.6.3.2 Impedance Phase Measurement
          3. 7.3.6.3.3 Impedance Magnitude Measurement
      7. 7.3.7 Protection and Monitoring
        1. 7.3.7.1 Over current Limit (ILIMIT)
        2. 7.3.7.2 Over current Shutdown (ISD)
        3. 7.3.7.3 DC Detect
        4. 7.3.7.4 Clip Detect
        5. 7.3.7.5 Global Over Temperature Warning (OTW), Over Temperature Shutdown (OTSD) and Thermal Foldback (TFB)
        6. 7.3.7.6 Channel Over Temperature Warning [OTW(i)] and Shutdown [OTSD(i)]
        7. 7.3.7.7 Thermal Foldback
        8. 7.3.7.8 Undervoltage (UV) and Power-On-Reset (POR)
        9. 7.3.7.9 Over Voltage (OV) and Load Dump
      8. 7.3.8 Power Supply
        1. 7.3.8.1 Power-Supply Sequence
      9. 7.3.9 Hardware Control Pins
        1. 7.3.9.1 FAULT
        2. 7.3.9.2 WARN
        3. 7.3.9.3 MUTE
        4. 7.3.9.4 STANDBY
    4. 7.4 Device Functional Modes
      1. 7.4.1 Operating Modes and Faults
    5. 7.5 Programming
      1. 7.5.1 I2C Serial Communication Bus
      2. 7.5.2 I2C Bus Protocol
      3. 7.5.3 Random Write
      4. 7.5.4 Sequential Write
      5. 7.5.5 Random Read
      6. 7.5.6 Sequential Read
  9. 8 Registers
    1. 8.1 Register Maps
      1. 8.1.1  Mode Control Register (address = 0x00) [default = 0x00]
      2. 8.1.2  Miscellaneous Control 1 Register (address = 0x01) [default = 0x32]
      3. 8.1.3  Miscellaneous Control 2 Register (address = 0x02) [default = 0x62]
      4. 8.1.4  Channel State Control Register (address = 0x04) [default = 0x55]
      5. 8.1.5  DC Load Diagnostic Control 1 Register (address = 0x09) [default = 0x00]
      6. 8.1.6  DC Load Diagnostic Control 2 Register (address = 0x0A) [default = 0x11]
      7. 8.1.7  DC Load Diagnostic Control 3 Register (address = 0x0B) [default = 0x11]
      8. 8.1.8  DC Load Diagnostic Report 1 Register (address = 0x0C) [default = 0x00]
      9. 8.1.9  DC Load Diagnostic Report 2 Register (address = 0x0D) [default = 0x00]
      10. 8.1.10 DC Load Diagnostics Report 3—Line Output—Register (address = 0x0E) [default = 0x00]
      11. 8.1.11 Channel State Reporting Register (address = 0x0F) [default = 0x55]
      12. 8.1.12 Channel Faults (Over current, DC Detection) Register (address = 0x10) [default = 0x00]
      13. 8.1.13 Global Faults 1 Register (address = 0x11) [default = 0x00]
      14. 8.1.14 Global Faults 2 Register (address = 0x12) [default = 0x00]
      15. 8.1.15 Warnings Register (address = 0x13) [default = 0x20]
      16. 8.1.16 Pin Control Register (address = 0x14) [default = 0x00]
      17. 8.1.17 AC Load Diagnostic Control 1 Register (address = 0x15) [default = 0x00]
      18. 8.1.18 AC Load Diagnostic Control 2 Register (address = 0x16) [default = 0x00]
      19. 8.1.19 AC Load Diagnostic Report Ch1 through CH4 Registers (address = 0x17–0x1A) [default = 0x00]
      20. 8.1.20 AC Load Diagnostic Report Phase High Register (address = 0x1B) [default = 0x00]
      21. 8.1.21 AC Load Diagnostic Report Phase Low Register (address = 0x1C) [default = 0x00]
      22. 8.1.22 AC Load Diagnostic Report STI High Register (address = 0x1D) [default = 0x00]
      23. 8.1.23 AC Load Diagnostic Report STI Low Register (address = 0x1E) [default = 0x00]
      24. 8.1.24 Miscellaneous Control 3 Register (address = 0x21) [default = 0x00]
      25. 8.1.25 Clip Control Register (address = 0x22) [default = 0x01]
      26. 8.1.26 Clip Warning Register (address = 0x24) [default = 0x00]
      27. 8.1.27 Current LIMIT Status Register (address = 0x25) [default = 0x00]
      28. 8.1.28 Fault and Warning Pin Control Register (address = 0x27) [default = 0x7F]
      29. 8.1.29 Thermal Foldback Control Register (address = 0x28) [default = 0x00]
      30. 8.1.30 AC Diagnostic Frequency Control Register (address = 0x2A) [default = 0x32]
      31. 8.1.31 SYNC PIN Control Register (address = 0x2B) [default = 0x02]
  10. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 AM Radio Avoidance
      2. 9.1.2 Parallel BTL Operation (PBTL)
      3. 9.1.3 Reconstruction Filter Design
      4. 9.1.4 Line Driver Applications
    2. 9.2 Typical Applications
      1. 9.2.1 BTL Application
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 Hardware Design
          2. 9.2.1.2.2 Bootstrap Capacitors
          3. 9.2.1.2.3 Output Reconstruction Filter
        3. 9.2.1.3 Application Curves
        4. 9.2.1.4 PBTL Application
          1. 9.2.1.4.1 Design Requirements
          2. 9.2.1.4.2 Detailed Design Procedure
            1. 9.2.1.4.2.1 Hardware Design
          3. 9.2.1.4.3 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
        1. 9.4.1.1 Electrical Connection of Thermal pad and Heat Sink
        2. 9.4.1.2 EMI Considerations
        3. 9.4.1.3 General Considerations
      2. 9.4.2 Layout Example
      3. 9.4.3 Thermal Considerations
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Electrostatic Discharge Caution
    4. 10.4 Glossary
    5. 10.5 Support Resources
    6. 10.6 Trademarks
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Package Option Addendum
      1. 12.1.1 Packaging Information
      2. 12.1.2 Tape and Reel Information

5.5 Electrical Characteristics

Test conditions (unless otherwise noted): TC = 25°C, PVDD = VBAT = 14.4 V, DVDD = 3.3 V, RL = 4Ω, Pout = 1 W/ch, ƒout = 1 kHz, Fsw = 2.1 MHz, AES17 Filter, reconstruction filter inductor used: DFEG7030D-3R3M from MuRata Toko, default I2C settings, see application diagram
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
OPERATING CURRENT
IPVDD_IDLE PVDD idle current All channels playing, no audio input 65 80 mA
IPVDD+VBAT_IDLE PVDD+VBAT idle current All channels playing, no audio input 155 190 mA
IVBAT_IDLE VBAT idle current All channels playing, no audio input 90 110 mA
IPVDD_STBY PVDD standby current STANDBYActive, DVDD= 0 V 0.08 μA
IVBAT_STBY VBAT standby current STANDBYActive, DVDD= 0 V 3.0 μA
ITOTAL_STBY PVDD+VBAT standby current STANDBYActive, DVDD = 0 V 3.0 7.0 μA
IDVDD DVDD supply current All channels playing, -60 dB Signal 6.2 7.0 mA
OUTPUT POWER
PO_BTL Output power per channel, BTL 4 Ω, PVDD = 14.4 V, THD+N = 1%, TC = 75°C 20 22 W
4 Ω, PVDD = 14.4 V, THD+N = 10%, TC = 75°C 24 27
PO_BTL Output power per channel, BTL 2 Ω, PVDD = 14.4 V, THD+N = 1%, TC = 75°C 31 38 W
2 Ω, PVDD = 14.4 V, THD+N = 10%, TC = 75°C 40 45
PO_BTL Output power per channel, BTL 4 Ω, PVDD = 18 V, THD+N = 1%, TC = 75°C 32 35 W
4 Ω, PVDD = 18 V, THD+N = 10%, TC = 75°C 40 44
PO_PBTL Output power per channel in parallel mode, PBTL 2 Ω, PVDD = 14.4 V, THD+N = 1%, TC = 75°C 40 44 W
2 Ω, PVDD = 14.4 V, THD+N = 10%, TC = 75°C 50 54
PO_PBTL Output power per channel in parallel mode, PBTL 1 Ω, PVDD = 14.4 V, THD+N = 1%, TC = 75°C 62 70 W
1 Ω, PVDD = 14.4 V, THD+N = 10%, TC = 75°C 78 85
PO_PBTL Output power per channel in parallel mode, PBTL 2 Ω, PVDD = 18 V, THD+N = 1%, TC = 75°C 63 68 W
2 Ω, PVDD = 18 V, THD+N = 10%, TC = 75°C 78 83
EFFP Power efficiency 4 channels operating, 25 W output power/ch 4 Ω load, PVDD = 14.4 V, TC = 25°C; (includes output
filter losses)		 86%
AUDIO PERFORMANCE
Vn Output Noise Voltage Zero input, A-weighting, 10 dB gain, PVDD = 14.4 V 42 μV
Zero input, A-weighting, 16 dB gain, PVDD = 14.4 V 48
Zero input, A-weighting, 22 dB gain, PVDD = 18 V 58
Zero input, A-weighting, 28 dB gain, PVDD = 18 V 79
Crosstalk Channel crosstalk PVDD = 14.4 Vdc + 1 VRMS, ƒ = 1 kHz 90 dB
PSRR Power-supply rejection ratio PVDD = 14.4 Vdc + 1 VRMS, ƒ = 1 kHz 75 dB
THD+N Total harmonic distortion + noise 0.01 %
G Gain Level 1 9.0 9.5 10.0 dB
Level 2 15.0 15.5 16.0
Level 3 (default) 21.0 21.5 22.0
Level 4 27.0 27.5 28.0
GCH Channel-to-channel gain variation –0.5 0 0.5 dB
GMUTE Output Attenuation Assert MUTE and compare to amp playing 1W audio
into 4 Ω		 100 110 dB
VCLICK Click & Pop Zero input, ITU-filter, 22dB gain, PVDD = 14.4 V 5 mV
LINE OUTPUT PERFORMANCE
Vn_LINEOUT LINE Output Noise Voltage Zero input, A-weighting, channel set to LINE MODE, PVDD = 14.4 V, RL = 600 Ω 42 μV
THD+N Line output Total harmonic distortion + noise VO = 2Vrms , channel set to LINE MODE, PVDD = 14.4 V 0.02 %
ANALOG INPUT PINS
RIN Input impedance 10 dB gain 80 kΩ
16 dB gain 40 kΩ
22 dB gain 20 kΩ
28 dB gain 10 kΩ
VIN Maximum input voltage swing,
Single Ended		 1 VRMS
Maximum input voltage swing,
Differential		 Positive input equals negative input 2
IIN Maximum input current ±1 mA
DIGITAL INPUT PINS
VIH Input logic level high 70 %DVDD
VIL Input logic level low 30
IIH Input logic current VI = DVDD 15 uA
IIL VI= 0 -15
PWM OUTPUT STAGE
RDS(on) FET drain-to-source resistance 25°C, Including bond wire and package resistance 120 mΩ
RDS(on) FET drain-to-source resistance 25°C, Not including bond wire and package resistance 90 mΩ
OVERVOLTAGE (OV) PROTECTION
VPVDD_OV PVDD overvoltage shutdown 18.5 21 23 V
VPVDD_OV_HYS PVDD overvoltage shutdown hysteresis 0.5 V
VVBAT_OV VBAT overvoltage shutdown 18.5 21 23 V
VVBAT_OV_HYS VBAT overvoltage shutdown hysteresis 0.5 V
UNDERVOLTAGE (UV) PROTECTION
VBATUV_SET  VBAT undervoltage shutdown set 4 4.5 V
VBATUV_CLEAR VBAT undervoltage shutdown clear 4.2
PVDDUV_SET PVDD undervoltage shutdown set 4 4.5
PVDDUV_CLEAR PVDD undervoltage shutdown clear 4.2
BYPASS VOLTAGES
VGVDD Gate Drive Bypass pin voltage 7 V
VAVDD Analog Bypass Pin Voltage 6
POWER-ON RESET (POR)
VPOR DVDD voltage for POR 1.8 2.1 V
VPOR_HY DVDD POR recovery hysteresis voltage 0.5
OVERTEMPERATURE (OT) PROTECTION
OTW(i) Channel Over-Temperature Warning 150 °C
OTSD(i) Channel Over-Temperature Shutdown 175
OTW Global Junction Over-Temperature Warning set by register 0x01 bit 5-6, default value 130
OTSD Global Junction Over-Temperature Shutdown 160
OTHYS Over-Temperature Hysterisis 15
LOAD OVER CURRENT PROTECTION
ILIM Overcurrent limit OC Level 1, Load current 4.8 A
OC Level 2, Load current 6 6.5
ISD Overcurrent Shutdown OC Level 1, Any short to supply, ground, or other channels 7
OC Level 2, Any short to supply, ground, or other channels 9
DC DETECT
DCFAULT Output DC Fault Protection PVDD = 14.4 V 2 2.5 V
DIGITAL OUTPUT PINS
VOH Output voltage for logic level high I = ±2mA 90 %DVDD
VOL Output voltage for logic level low 10
SYNC
fsync Supported SYNC Frequencies, controller mode Reg 0x02 bit 6-4: 101   1.8   Mhz
Reg 0x02 bit 6-4: 110   2.1   Mhz
Reg 0x02 bit 6-4: 111   2.3   Mhz
Δfsync Supported SYNC Frequency
deviation, target mode		 -10 10 %
Dsync Supported SYNC dutycycle,
target mode		 45% 50% 55%
LOAD DIAGNOSTICS
S2P Maximum resistance to detect a short from OUT pin(s) to PVDD 500 Ω
S2G Maximum resistance to detect a short from OUT pin(s) to ground 200
SL Shorted Load Detection Tolerance RL = 4 Ω, Other Channels in Hi-Z ±0.5
OL Minimum Impedance Detected as Open Load Other Channels in Hi-Z 70
TDC_DIAG DC Diagnostic time 4 channels, no faults 231 ms
LO Line Output Maximum
Detectable Impedance		 For load resistance below this value, the device will
report the LO load		 6 kΩ
TLINE_DIAG Line output Diagnostic time 40 ms
ACIMP AC Impedance Accuracy ƒ = 19 kHz, RL = 4 Ω ±0.75 Ω
ZOUT (including LC filter), ƒ = 19 kHz 25%
TAC_DIAG AC Diagnostic time 4 channels, ƒ = 19 kHz 550 ms
FAC AC Diagnostic Test frequency Default 18.75 kHz
I2C_ADDR PINS
tI2C_ADDR Time delay needed for I2C Address set-up From release of Standby pin until Address set-up 300 μs
I2C CONTROL PORT
tBUS Bus free time between start and stop conditions 1.3 μs
tHOLD1 Hold Time, SCL to SDA 0 ns
tHOLD2 Hold Time, start condition to SCL 0.6 μs
tSTART I2C Startup Time After DVDD Power On Reset 12 ms
tRISE Rise Time, SCL and SDA 300 ns
tFALL Fall Time, SCL and SDA 300 ns
tSU1 Setup, SDA to SCL 100 ns
tSU2 Setup, SCL to Start Condition 0.6 μs
tSU3 Setup, SCL to Stop Condition 0.6 μs
tW(H) Required Pulse Duration SCL "High" 0.6 μs
tW(L) Required Pulse Duration SCL "Low" 1.3 μs