SLUSBX9J March   2014  – October 2026 TPS23861

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Switching Characteristics
    8. 5.8 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
      1. 6.1.1 Detailed Pin Description
      2. 6.1.2 I2C Detailed Pin Description
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1  Detection Resistance Measurement
      2. 6.3.2  Physical Layer Classification
      3. 6.3.3  Class and Detect Fields
      4. 6.3.4  Register State Following a Fault
      5. 6.3.5  Disconnect
      6. 6.3.6  Disconnect Threshold
      7. 6.3.7  Fast Shutdown Mode
      8. 6.3.8  Legacy Device Detection
      9. 6.3.9  VPWR Undervoltage and UVLO Events
      10. 6.3.10 Timer-Deferrable Interrupt Support
      11. 6.3.11 A/D Converter and I2C Interface
      12. 6.3.12 Independent Operation when the AUTO Bit is Set
      13. 6.3.13 I2C Slave Address and AUTO Bit Programming
    4. 6.4 Device Functional Modes
      1. 6.4.1 Off
      2. 6.4.2 Manual
      3. 6.4.3 Semi-Auto
      4. 6.4.4 Auto
      5. 6.4.5 Push-Button Power On Response
      6. 6.4.6 TSTART Indicators of Detect and Class Failures
      7. 6.4.7 Device Power On Initialization
    5. 6.5 Register Map – I2C-Addressable
      1. 6.5.1  Interrupt Register
      2. 6.5.2  Interrupt Enable Register
      3. 6.5.3  Power Event Register
      4. 6.5.4  Detection Event Register
      5. 6.5.5  Fault Event Register
      6. 6.5.6  Start/ILIM Event Register
      7. 6.5.7  Supply Event Register
      8. 6.5.8  Port n Status Register
        1. 6.5.8.1 Port 1 Status Register
        2. 6.5.8.2 Port 2 Status Register
        3. 6.5.8.3 Port 3 Status Register
        4. 6.5.8.4 Port 4 Status Register
      9. 6.5.9  Power Status Register
      10. 6.5.10 I2C Slave Address Register
      11. 6.5.11 Operating Mode Register
      12. 6.5.12 Disconnect Enable Register
      13. 6.5.13 Detect/Class Enable Register
      14. 6.5.14 Port Power Priority Register
      15. 6.5.15 Timing Configuration Register
      16. 6.5.16 General Mask 1 Register
      17. 6.5.17 Detect/Class Restart Register
      18. 6.5.18 Power Enable Register
      19. 6.5.19 Reset Register
      20. 6.5.20 Legacy Detect Mode Register
      21. 6.5.21 Two-Event Classification Register
      22. 6.5.22 Interrupt Timer Register
      23. 6.5.23 Disconnect Threshold Register
        1. 6.5.23.1 Bits Description
      24. 6.5.24 ICUTnm CONFIG Register
        1. 6.5.24.1 ICUT21 CONFIG Register
        2. 6.5.24.2 ICUT43 CONFIG Register
        3. 6.5.24.3 Bits Description
      25. 6.5.25 Temperature Register
      26. 6.5.26 Input Voltage Register
      27. 6.5.27 Port n Current Register
        1. 6.5.27.1 Port 1 Current Register
        2. 6.5.27.2 Port 2 Current Register
        3. 6.5.27.3 Port 3 Current Register
        4. 6.5.27.4 Port 4 Current Register
      28. 6.5.28 Port n Voltage Register
        1. 6.5.28.1 Port 1 Voltage Register
        2. 6.5.28.2 Port 2 Voltage Register
        3. 6.5.28.3 Port 3 Voltage Register
        4. 6.5.28.4 Port 4 Voltage Register
      29. 6.5.29 PoE Plus Register
      30. 6.5.30 Firmware Revision Register
      31. 6.5.31 I2C Watchdog Register
      32. 6.5.32 Device ID Register
      33. 6.5.33 Cool Down/Gate Drive Register
      34. 6.5.34 Port n Detect Resistance Register
        1. 6.5.34.1 Port 1 Detect Resistance Register
          1. 6.5.34.1.1 Port 2 Detect Resistance Register
          2. 6.5.34.1.2 Port 3 Detect Resistance Register
          3. 6.5.34.1.3 Port 4 Detect Resistance Register
      35. 6.5.35 Port n Detect Voltage Difference Register
        1. 6.5.35.1 Port 1 Detect Voltage Difference Register
        2. 6.5.35.2 Port 2 Detect Voltage Difference Register
        3. 6.5.35.3 Port 3 Detect Voltage Difference Register
        4. 6.5.35.4 Port 4 Detect Voltage Difference Register
      36. 6.5.36 Reserved Registers
  8. 7 Application and Implementation
    1. 7.1 Introduction to PoE
    2. 7.2 Application Information
      1. 7.2.1 Kelvin Current Sensing Resistor
      2. 7.2.2 Connections on Unused Ports
    3. 7.3 Typical Application
      1. 7.3.1 Two Port, Auto Mode Application with External Port Reset
        1. 7.3.1.1 Design Requirements
      2. 7.3.2 Four Port, Auto Mode Application
        1. 7.3.2.1 Design Requirements
      3. 7.3.3 Eight Port, Semi-Auto Mode Application Using MSP430 Micro-Controller
        1. 7.3.3.1 Design Requirements
      4. 7.3.4 Detailed Design Procedure
        1. 7.3.4.1 Power Pin Bypass Capacitors
        2. 7.3.4.2 Per Port Components
        3. 7.3.4.3 System Level Components (not shown in the schematic diagrams)
      5. 7.3.5 Application Curves
    4. 7.4 System Examples
      1. 7.4.1 Overcurrent and Overload Protection
      2. 7.4.2 Inrush Protection
      3. 7.4.3 ICUT Current Limit
      4. 7.4.4 Foldback Protection (ILIM)
      5. 7.4.5 Kelvin Current Sensing Resistor
    5. 7.5 Power Supply Recommendations
      1. 7.5.1 VDD
      2. 7.5.2 VPWR
      3. 7.5.3 VPWR-RESET Sequencing
    6. 7.6 Layout
      1. 7.6.1 Layout Guidelines
        1. 7.6.1.1 Port Current Kelvin Sensing
      2. 7.6.2 Layout Example
        1. 7.6.2.1 Component Placement and Routing Guidelines
          1. 7.6.2.1.1 Power Pin Bypass Capacitors
          2. 7.6.2.1.2 Per-Port Components
  9. 8 Device and Documentation Support
    1. 8.1 Documentation Support
      1. 8.1.1 Related Documentation
    2. 8.2 Receiving Notification of Documentation Updates
    3. 8.3 Support Resources
    4. 8.4 Trademarks
    5. 8.5 Electrostatic Discharge Caution
    6. 8.6 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

6.3.12 Independent Operation when the AUTO Bit is Set

The TPS23861 operates as a fully automatic PSE in compliance with IEEE 802.3at when the AUTO bit is set as described in Section 6.3.13 section. Fully automatic operation means that the TPS23861 operates as a power-over-ethernet four-port PSE without any connection to a host system via the I2C bus. Generally speaking, when the bit is set, most specialized features of the TPS23861 are disabled.

Note:

The state of the AUTO bit is read only following power on, hardware reset ( RESET pin) or writing a 1 to the RESAL bit in the Reset Register.

If the AUTO bit is set and the TPS23861 is connected to a host over the I2C bus, the host may change the register settings any time after power up, including changing operating mode. When the AUTO bit is set, the state of TPS23861 following power up is summarized below.

  • The CLEn and DETn bits in the Detect/Class Enable Register is set. Consequently, detect and classification is performed before any power on.
  • The DCDEn bit in the Disconnect Enable Register is set, enabling automatic disconnection.
  • The TECLENn bits in the Two-Event Classification Register is set to 0b01. Consequently, if a Class 4 PD is recognized during the classification cycle,
    • The TPS23861 initiates a second physical-layer classification event.
    • The PoEPn bit in the PoE Plus register is set, employing the 2x curve for ILIM.
    • The ICUT Port n fields in the ICUTnm CONFIG registers will be set to 0b110 corresponding to 645mA.
  • If a Class 0, 1, 2 or 3 PD is recognized during the classification cycle,
    • There is no second physical-layer classification event.
    • The POEPn bit is cleared so the TPS23861 employs the 1x foldback curve for ILIM.
    • A value of 374mA is used for ICUT.
  • The Port n Mode field in the Operating Mode Register is set to Auto (0×11) for all four ports. Consequently,
    • Detection, classification and power up occurs in sequence, automatically and independently for each port.
    • Following a valid one- or two-event physical layer classification, the TPS23861 applies power to a port subject to the inrush-current foldback protection curve in Figure 7-12.
    .
  • The FSEn bits in the Port Power Priority Register is set. Consequently, all ports are shut down in response to a low level on the SHTDWN pin.
  • The LEGMODn fields in the Legacy Detect Mode Register is set to 00. Consequently, legacy PD devices not compliant with IEEE 802.3at will not be detected.
  • The General Mask 1 Register is set to its standard power-on-reset value 0x80. Consequently,
    • Interrupts are enabled.
    • During detection A/D conversions of the detect voltage occurs at a rate of 800 per second.
    • Classification levels are determined as if a 255mΩ resistor is used for the current-sense resistor.
    Note:

    If a 250mΩ resistor is used, the classification thresholds shifts slightly, but remains compliant with IEEE 802.3at.

  • The Interrupt Enable Register is set to 0xE4, enabling the following interrupts
    • SUPEN – Supply event fault enable bit.
    • STRTEN – Start fault enable bit.
    • IFEN – ICUT or ILIM fault enable bit.
    • DISEN – Disconnect event interrupt enable bit.
  • Any register not explicitly referenced above is set to its default power-on-reset value according to Table 6-10.