The ENA input pin and Power-Good output pin on the primary-side support both TTL and CMOS logic levels in 5V or 3.3V domain. The active-high enable input (ENA) pin is used to turn-on the isolated DC/DC converter. Either 3.3V or 5V logic rail can be used. The recommended maximum ENA-pin voltage is 5.5V. After ENA pin voltage rises above the enable threshold V_{ENA_R}, the power module starts switching, goes through the soft-start process and delivers power to the secondary side. After ENA pin voltage falls below the disable threshold V_{ENA_F}, UCC34141-Q1 is disabled, and the internal power stage stops switching.

For Latch-off devices, the ENA pin can also be used to reset the device after it enters the protection safe-state mode. After a detected fault, the protection logic will latch off and place the device into a safe state. To reset the part, the user is required to wait for t_{EN_LO_DLY} after fault, then toggle the ENA-pin voltage below V_{ENA_F} for longer than t_{EN_LO_RST}, then toggle back up to 3.3V or 5V. The device will then exit the latch-off mode and a soft-start sequence will be reinitiated.

The ENA pin can also be used to implement a programmable input UVLO by using an external resistor divider between VIN and ENA pins. For the device and application with relatively low input UVLO and relatively high V_IN, when there is a slow V_IN ramp during start-up, the relatively low transformer turns-ratio will not be able to generate enough power to charge up the output capacitor and will thus fail the start-up. This issue can be solved by adding a resistor divider between VIN, ENA, and GNDP pins to program the ENA signal time and override the internal input UVLO. The V_{ENA_R} rising threshold is set at 1.5V and the V_{ENA_F} falling threshold is set at 1.35V. The programmable input UVLO feature can also be used to sequentially start-up multiple integrated DC/DC modules, by adding delay capacitors between ENA and GNDP pins to program the delay time between each power module. Specifically, the ENA1 signal can enable one module or one grouped modules, while the delayed ENA2 signal from ENA1 can sequentially enable another module or another grouped modules. For the appliation where ENA1 and ENA2 are too far away for the R_ENA2 routing, the RC circuitry for ENA1 can be duplicated at the ENA pin of each module to enable sequential startup. If the sequential power up is not needed, multiple modules can share the same resistor divider to program input UVLO threshold. To facilitate the implementation, the recommended resistor and capacitor values are available in a calculation tool, as another design supporting document besides this datasheet.

If a single fault event on the resistor divider needs to be considered, e.g. the single bottom resistor is failed open, the risk of exceeding the 7V absolute maximum of ENA pin needs to be mitigated in application level. Two approaches can be applied: one option is adding an external Zener diode on ENA pin; another option is to split the bottom resistance into two resistor components.

The Power-Good is an open-drain output which active state indicates when the module has no fault and the output voltages are within ±10% of the output voltage regulation setpoints. To account for the maximum current sinking capability of the internal pull-down MOSFET < 5mA, a pull-up resistor (> 1kΩ) from Power-Good pin to either a 5V or 3.3V logic rail is recommended. Higher resistance will reduce the quiescent current in normal logic state of Power-Good pin. It is essential to maintain the Power-Good pin voltage below 5.5V without exceeding its recommended operating voltage.

For Active-Low Power-Good polarity, there is a voltage drop in the PG signal during start up, due to the parasitic capacitance between the adjacent VIN pin and PG pin. This capacitive coupling generates a pulling currect into the PG pin and therefore leads to a volage drop across the pull-up resistor and thus a voltage drop on PG signal during start up. A 4.99kΩ pull-up resistor, and a 1μF decoupling capacitor connecting PG pin and ground are recommended to diminish the voltage drop during start up.

For Active-High Power-Good polarity, the PG will be grounded during the start up, so a small decoupling capacitor in the range of 0.1μF - 1μF with a 10kΩ pull-up resistor can be selected. The active-high setting allows an easy group fault reporting by direct connection of the PG pin signals from multiple DC/DC modules, becasue the combined PG signal will stay low when a power-bad condition in any one (or more) module(s) turns-on the pull-down FET; during power-good condition on the other hand, the combined PG signal will stay high becasue the pull-down FETs of all the DC/DC modules stay off