SLUSFP1B April   2025  – November 2025 UCC34141-Q1

ADVANCE INFORMATION  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Insulation Specifications
    6. 6.6 Electrical Characteristics
    7. 6.7 Safety-Related Certifications
    8. 6.8 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Power Stage Operation
        1. 7.3.1.1 VDD-COM Voltage Regulation
        2. 7.3.1.2 COM-VEE Voltage Regulation
        3. 7.3.1.3 COM-VEE Output Capability
      2. 7.3.2 Output Voltage Soft Start
      3. 7.3.3 ENA and Power-Good
      4. 7.3.4 Protection Functions
        1. 7.3.4.1 Input Undervoltage Lockout
        2. 7.3.4.2 Input Overvoltage Lockout
        3. 7.3.4.3 Output Undervoltage Protection
        4. 7.3.4.4 Output Overvoltage Protection
        5. 7.3.4.5 Over-Temperature Protection
        6. 7.3.4.6 BSW Pin Faults Protection
    4. 7.4 Device Functional Modes
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 VDD-COM Voltage Regulation
        2. 8.2.2.2 COM-VEE Voltage Regulation and Single Output Configuration
    3. 8.3 System Examples
    4. 8.4 Power Supply Recommendations
    5. 8.5 Layout
      1. 8.5.1 Layout Guidelines
      2. 8.5.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Third-Party Products Disclaimer
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 Receiving Notification of Documentation Updates
    4. 9.4 Support Resources
    5. 9.5 Trademarks
    6. 9.6 Electrostatic Discharge Caution
    7. 9.7 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information
    1. 11.1 Packaging Information
    2. 11.2 Tape and Reel Information
    3. 11.3 Mechanical Data

7.1 Overview

The UCC34141-Q1 device is suitable for applications that have limited board space and require more integration. It is also suitable for very-high voltage applications, where power transformers meeting the required isolation specifications are bulky and expensive. The low-profile, low-center of gravity, and low weight provides a higher vibration tolerance than systems using large bulky transformers. The device is easy-to-use and provides flexibility to adjust both positive and negative output voltages as needed when optimizing the gate voltage for maximum efficiency while also protecting gate oxide from over-stress with its tight voltage regulation accuracy.

The device integrates a high-efficiency, low-emissions, isolated DC/DC converter for powering the gate drive of SiC or IGBT power devices in traction inverter motor drives, on-board-charger (OBC), server telecom rectifiers, industrial motor drives, or other high voltage DC/DC converters. This DC/DC converter can provide greater than 1.5W of power.

The integrated DC/DC converter uses switched mode operation and proprietary circuit techniques to reduce power losses and boost efficiency. Specialized control mechanisms, clocking schemes, and the use of an on- chip transformer provide high efficiency and low radiated emissions.

The integrated transformer provides power delivery throughout a wide temperature range while maintaining a 5000VRMS isolation, and an 1202VRMS continuous working voltage. The low isolation capacitance of the transformer provides high CMTI allowing fast dv/dt switching and higher switching frequencies, while emitting less noise.

The VIN supply is provided to the primary-side power controller that switches the input stage connected to the integrated transformer. Power is transferred to the secondary-side output stage, and regulated to a level set by the resistor divider connected between the VDD pin and the FBVDD pin with respect to the COMA pin. The output voltage is adjustable with external resistor divider allowing a wide (VDD – COM) range.

For optimal performance ensure to maintain the VVIN input voltage within the recommended operating voltage range. Do not exceed the absolute maximum voltage rating to avoid over-stressing the input pins.

A fast hysteretic feedback burst control loop monitors (VDD – COM) and ensures the output voltage is kept within the hysteresis with low overshoot and undershoot during load and line transients. The burst control loop enables efficient operation across full load and allows a wide output voltage adjustability throughout the whole VVIN range. The undervoltage lockout (UVLO) protection monitors the input voltage pin, VIN, with hysteresis and input filter ensuring robust system performance under noisy conditions. The overvoltage lockout (OVLO) protection monitors the input voltage pin, VIN, to protect against over-voltage stress by disabling switching and reducing the internal peak voltage. Controlled soft-start timing, provided throughout the full power-up time, limits the peak input inrush current while charging the output capacitor and load.

The UCC34141-Q1 can also provide a second output rail, (COM – VEE), that is used as a negative bias for the gate drivers allowing quicker turn-off switching for the IGBTs and also to protect from unwanted turn-on during fast switching of SiC devices. (COM – VEE) has a simple yet fast and efficient bias controller to ensure the positive and negative rails are regulated during the PWM switching. In this case, COM pin is used as the common reference point. The COM pin connects to the source of SiC device or emitter of an IGBT device.

A fault protection and Power-Good status pin provides a mechanism for the host controller to monitor the status of the DC/DC converter and provide proper sequencing of power and PWM control signals to the gate driver. Fault protection includes undervoltage, overvoltage, over-temperature shutdown, and isolated channel communication interface watchdog timer.

A typical soft-start ramp-up time is lower than tSSTO, and varies based on input voltage, output voltage, output capacitance, and load. If either output is shorted or over-loaded, the device will not be able to power-up within the tSSTO soft-start time, so the device will shut down. The fault response of the device varies based on the part number as listed in Table 4-1. For latch-off operation, the device will shut down and latches-off for protection and can be reset by toggling the ENA pin or resetting VVIN. For auto-restart operation the device shuts down and an auto-restart timer of tRESTART will start afterwords, and then the part will attempt to auto-restart after that timer expires. If the fault has been removed, the part will soft-start to regulation successfullly. If the fault condition remains, the part will shut down again and attempt another auto-restart. The device can continuously operate safely in hiccup mode as long as the fault occurs.

The UCC34141-Q1 has a Power-Good indicator with active polarity either High or Low based on the he part number as listed in Table 4-1. The output load must be kept low until start-up is complete and Power-Good pin becomes Active. For succesful soft-start, do not apply a heavy load to (VDD – COM) or (COM – VEE) outputs until the Power-Good pin has indicated Active status.

TI recommends to use the Power-Good status indicator as a trigger point to start the PWM signal into the gate driver. Power-Good output removes any ambiguity as to when the outputs are ready by providing a robust closed loop indication of when both (VDD –COM) and (COM – VEE) outputs have reached their regulation threshold within ±10%.

Do not allow the host to begin PWM to gate driver until Power-Good goes Active. This action typically occurs less than tSSTO after VVIN > VVIN_UVLOP and ENA goes high. The Power-Good status output indicates the power is good after soft-start of (VDD – COM) and (COM – VEE) and are within ±10% of regulation.

If the host is not monitoring Power-Good, it is recommended that the host disables PWM to gate driver until 50 ms after VVIN > VVIN_UVLOP and ENA goes high in order to allow enough time for power to be good after soft-start of VDD and VEE.