SLUSFP1B April   2025  – November 2025 UCC34141-Q1

ADVANCE INFORMATION  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Insulation Specifications
    6. 6.6 Electrical Characteristics
    7. 6.7 Safety-Related Certifications
    8. 6.8 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Power Stage Operation
        1. 7.3.1.1 VDD-COM Voltage Regulation
        2. 7.3.1.2 COM-VEE Voltage Regulation
        3. 7.3.1.3 COM-VEE Output Capability
      2. 7.3.2 Output Voltage Soft Start
      3. 7.3.3 ENA and Power-Good
      4. 7.3.4 Protection Functions
        1. 7.3.4.1 Input Undervoltage Lockout
        2. 7.3.4.2 Input Overvoltage Lockout
        3. 7.3.4.3 Output Undervoltage Protection
        4. 7.3.4.4 Output Overvoltage Protection
        5. 7.3.4.5 Over-Temperature Protection
        6. 7.3.4.6 BSW Pin Faults Protection
    4. 7.4 Device Functional Modes
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 VDD-COM Voltage Regulation
        2. 8.2.2.2 COM-VEE Voltage Regulation and Single Output Configuration
    3. 8.3 System Examples
    4. 8.4 Power Supply Recommendations
    5. 8.5 Layout
      1. 8.5.1 Layout Guidelines
      2. 8.5.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Third-Party Products Disclaimer
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 Receiving Notification of Documentation Updates
    4. 9.4 Support Resources
    5. 9.5 Trademarks
    6. 9.6 Electrostatic Discharge Caution
    7. 9.7 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information
    1. 11.1 Packaging Information
    2. 11.2 Tape and Reel Information
    3. 11.3 Mechanical Data

6.5 Insulation Specifications

PARAMETER TEST CONDITIONS VALUE UNIT
General
CLR External clearance (1) Shortest terminal-to-terminal distance through air > 8.2 mm
CPG External creepage (1) Shortest terminal-to-terminal distance across the package surface > 8.2 mm
DTI Distance through the insulation Minimum internal gap (internal clearance – transformer power isolation) > 70 µm
CTI Comparative tracking index DIN EN 60112 (VDE 0303-11); IEC 60112 > 600 V
Material group According to IEC 60664-1 I
Overvoltage category Rated mains voltage ≤ 300VRMS I-IV
Rated mains voltage ≤ 600VRMS I-IV
Rated mains voltage ≤ 1000VRMS I-III
DIN EN IEC 60747-17 (VDE 0884-17) (Planned Certification Targets) (2)
VIORM Maximum repetitive peak isolation voltage AC voltage (bipolar) 1700 VPK
VIOWM Maximum working isolation voltage AC voltage (sine wave) Time dependent dielectric breakdown (TDDB) test 1202 VRMS
DC voltage 1700 VDC
VIOTM Maximum transient isolation voltage VTEST = VIOTM, t = 60s (qualification); VTEST = 1.2 × VIOTM, t = 1s (100% production) 7071 VPK
VIMP Maximum impulse voltage (3) Tested in air, 1.2/50μs waveform per IEC 62368-1 8000 VPK
VIOSM Maximum surge isolation voltage (3) VIOSM ≥ 1.3 × VIMP; Tested in oil (qualification test), 1.2/50µs waveform per IEC 62368-1 10400 VPK
qpd Apparent charge (4) Method a: After I/O safety test subgroup 2/3, Vini = VIOTM, tini = 60s; Vpd(m) = 1.2 × VIORM, tm = 10s ≤ 5 pC
Method a: After environmental tests subgroup 1, Vini = VIOTM, tini = 60s; Vpd(m) = 1.6 × VIORM, tm = 10s ≤ 5 pC
Method b1: At routine test (100% production), Vini = 1.2 × VIOTM, tini = 1s; Vpd(m) = 1.875 × VIORM, tm = 1s ≤ 5 pC
CIO Barrier capacitance, input to output (5) VIO = 0.4 sin (2πft), f = 1MHz < 3 pF
RIO Isolation resistance, input to output (5) VIO = 500V, TA = 25°C > 1012 Ω
VIO = 500V, 100°C ≤ TA ≤ 125°C > 1011 Ω
VIO = 500V at TS = 150°C > 109 Ω
Pollution degree 2
Climatic category 40/125/21
UL 1577 (Planned Certification Target)
VISO Withstand isolation voltage VTEST = VISO = 5000VRMS, t = 60s (qualification); VTEST = 1.2 × VISO = 6000VRMS, t = 1s (100% production) 5000 VRMS
(1) Creepage and clearance requirements should be applied according to the specific equipment isolation standards of an application. Care should be taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of the isolator on the printed-circuit board do not reduce this distance. Creepage and clearance on a printed-circuit board become equal in certain cases. Techniques such as inserting grooves and/or ribs on a printed-circuit board are used to help increase these specifications.
(2) This coupler is suitable for safe electrical insulation only within the maximum operating ratings. Compliance with the safety ratings shall be ensured by means of suitable protective circuits.
(3) Testing is carried out in air to determine the surge immunity of the package. Testing is carried out in oil to determine the intrinsic surge immunity of the isolation barrier.
(4) Apparent charge is electrical discharge caused by a partial discharge (pd).
(5) All pins on each side of the barrier tied together creating a two-terminal device.