SLUUDD2 User guide

SLUUDD2 June 2026 TPS65214

5.4 Configuring Sequence

The process to configure the PMIC sequence consist of the following two steps:

Power-up/Power-down slot assignment: The slot assignment defines the order in which rails turn ON or OFF. Each of the PMIC rails must have a slot assigned. There are 16 slots available (0-15). Multiple rails (including GPIOs) can be assigned to the same slot so they be enabled at the same time.
Power-up/Power-down slot duration: The slot duration is the timing between the start of one slot to the start of the next slot. For example, if Buck1 is assigned to slot0 with a 3ms duration and Buck2 is assigned to slot 1, then Buck2 turns ON 3ms after Buck1.

Note: The slot duration does not dictate how long it takes for the rails to ramp. The slot duration only specifies how long the PMIC waits before enabling (or disabling) the rails that were assigned to the next slot.

Table 5-7, Table 5-8, Table 5-9 and Table 5-10 show the register fields to be written when referring to the register map.

Table 5-7 Power-Up Sequence - Slot Assignments

	Register Address	Bit		Settings
	Register Address	Bit#	Field Name	Settings
Power-up Sequence Slot Assignment	0x11	7-4	BUCK1_SEQUENCE_ON_SLOT	see register map on data sheet
	0x10	7-4	BUCK2_SEQUENCE_ON_SLOT	see register map on data sheet
	0xF	7-4	BUCK3_SEQUENCE_ON_SLOT	see register map on data sheet
	0xE	7-4	LDO1_SEQUENCE_ON_SLOT	see register map on data sheet
	0xD	7-4	LDO2_SEQUENCE_ON_SLOT	see register map on data sheet
	0xC	7-4	LDO3_SEQUENCE_ON_SLOT	see register map on data sheet
	0xB	7-4	LDO4_SEQUENCE_ON_SLOT	see register map on data sheet
	0x15	7-4	GPO1_SEQUENCE_ON_SLOT	see register map on data sheet
	0x14	7-4	GPO2_SEQUENCE_ON_SLOT	see register map on data sheet
	0x13	7-4	GPIO_SEQUENCE_ON_SLOT	see register map on data sheet
	0x12	7-4	nRST_SEQUENCE_ON_SLOT	see register map on data sheet

Table 5-8 Power-Up Sequence - Slot Duration

	Register Address	Bit		Settings
	Register Address	Bit#	Field Name	Settings
Power-up Sequence Slot Duration	0x16	7-6	POWER_UP_SLOT_0_DURATION	see register map on data sheet
		5-4	POWER_UP_SLOT_1_DURATION	see register map on data sheet
		3-2	POWER_UP_SLOT_2_DURATION	see register map on data sheet
		1-0	POWER_UP_SLOT_3_DURATION	see register map on data sheet
	0x17	7-6	POWER_UP_SLOT_4_DURATION	see register map on data sheet
		5-4	POWER_UP_SLOT_5_DURATION	see register map on data sheet
		3-2	POWER_UP_SLOT_6_DURATION	see register map on data sheet
		1-0	POWER_UP_SLOT_7_DURATION	see register map on data sheet
	0x18	7-6	POWER_UP_SLOT_8_DURATION	see register map on data sheet
		5-4	POWER_UP_SLOT_9_DURATION	see register map on data sheet
		3-2	POWER_UP_SLOT_10_DURATION	see register map on data sheet
		1-0	POWER_UP_SLOT_11_DURATION	see register map on data sheet
	0x19	7-6	POWER_UP_SLOT_12_DURATION	see register map on data sheet
		5-4	POWER_UP_SLOT_13_DURATION	see register map on data sheet
		3-2	POWER_UP_SLOT_14_DURATION	see register map on data sheet
		1-0	POWER_UP_SLOT_15_DURATION	see register map on data sheet

Table 5-9 Power-Down Sequence - Slot Assignments

	Register Address	Bit		Settings
	Register Address	Bit#	Field Name	Settings
Power-down Sequence Slot Assignment	0x11	7-4	BUCK1_SEQUENCE_OFF_SLOT	see register map on data sheet
	0x10	7-4	BUCK2_SEQUENCE_OFF_SLOT	see register map on data sheet
	0xF	7-4	BUCK3_SEQUENCE_OFF_SLOT	see register map on data sheet
	0xE	7-4	LDO1_SEQUENCE_OFF_SLOT	see register map on data sheet
	0xD	7-4	LDO2_SEQUENCE_OFF_SLOT	see register map on data sheet
	0xC	7-4	LDO3_SEQUENCE_OFF_SLOT	see register map on data sheet
	0xB	7-4	LDO4_SEQUENCE_OFF_SLOT	see register map on data sheet
	0x15	7-4	GPO1_SEQUENCE_OFF_SLOT	see register map on data sheet
	0x14	7-4	GPO2_SEQUENCE_OFF_SLOT	see register map on data sheet
	0x13	7-4	GPIO_SEQUENCE_OFF_SLOT	see register map on data sheet
	0x12	7-4	nRST_SEQUENCE_OFF_SLOT	see register map on data sheet

Table 5-10 Power-Down Sequence - Slot Duration

	Register Address	Bit		Settings
	Register Address	Bit#	Field Name	Settings
Power-down Sequence Slot Duration	0x1A	7-6	POWER_DOWN_SLOT_0_DURATION	see register map on data sheet
		5-4	POWER_DOWN_SLOT_1_DURATION	see register map on data sheet
		3-2	POWER_DOWN_SLOT_2_DURATION	see register map on data sheet
		1-0	POWER_DOWN_SLOT_3_DURATION	see register map on data sheet
	0x1B	7-6	POWER_DOWN_SLOT_4_DURATION	see register map on data sheet
		5-4	POWER_DOWN_SLOT_5_DURATION	see register map on data sheet
		3-2	POWER_DOWN_SLOT_6_DURATION	see register map on data sheet
		1-0	POWER_DOWN_SLOT_7_DURATION	see register map on data sheet
	0x1C	7-6	POWER_DOWN_SLOT_8_DURATION	see register map on data sheet
		5-4	POWER_DOWN_SLOT_9_DURATION	see register map on data sheet
		3-2	POWER_DOWN_SLOT_10_DURATION	see register map on data sheet
		1-0	POWER_DOWN_SLOT_11_DURATION	see register map on data sheet
	0x1D	7-6	POWER_DOWN_SLOT_12_DURATION	see register map on data sheet
		5-4	POWER_DOWN_SLOT_13_DURATION	see register map on data sheet
		3-2	POWER_DOWN_SLOT_14_DURATION	see register map on data sheet
		1-0	POWER_DOWN_SLOT_15_DURATION	see register map on data sheet