SLUUDD2 June   2026 TPS65214

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2Hardware Requirements for NVM Programming
  6. 3Typical NVM Flow
  7. 4Programming Instructions
    1. 4.1 Connecting to the I2C address
  8. 5Register Configuration
    1. 5.1  Configuring Enable Settings
    2. 5.2  Configuring the Bucks
    3. 5.3  Configuring LDOs
    4. 5.4  Configuring Sequence
    5. 5.5  Configuring GPIOs
    6. 5.6  Configuring Multi-Function Pins
    7. 5.7  Configuring the EN/PB/VSENSE Pin
    8. 5.8  Changing I2C Address
    9. 5.9  Configuring Mask Settings
    10. 5.10 Exporting an NVM Configuration File
    11. 5.11 Loading a NVM Configuration File to PMIC
  9. 6NVM Programming
  10. 7Non-NVM Registers
  11. 8TPS6521405 default settings
  12.   A References

8 TPS6521405 default settings

The user-programmable TPS6521405VAFR variant comes with all Bucks, LDOs and GPIOs disabled by default and the corresponding output voltage registers set to the lowest values. All register settings are configured as 0h except the fields listed in the tables below.

Table 8-1 TPS6521405VAFR NVM registers NOT configured as 0h
Register AddressField NameValueDescription
0x00TI_DEV_ID0x44TPS6521405 identifier
0x01NVM_ID0x05TPS6521405 identifier
0x26I2C_ADDRESS_REG0x30I2C address upon reprogramming set to 0x30 by default
Table 8-2 TPS6521405VAFR non-NVM registers NOT configured as 0h
Register AddressField NameValueDescription
0x28MANUFACTURING_VERXSilicon Revision version.

0x01 = Revision 1,

0x02 = Revision 2,

...

0x2ADISCHARGE_CONFIG0x37Discharge enabled