SLUUDD2 June   2026 TPS65214

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2Hardware Requirements for NVM Programming
  6. 3Typical NVM Flow
  7. 4Programming Instructions
    1. 4.1 Connecting to the I2C address
  8. 5Register Configuration
    1. 5.1  Configuring Enable Settings
    2. 5.2  Configuring the Bucks
    3. 5.3  Configuring LDOs
    4. 5.4  Configuring Sequence
    5. 5.5  Configuring GPIOs
    6. 5.6  Configuring Multi-Function Pins
    7. 5.7  Configuring the EN/PB/VSENSE Pin
    8. 5.8  Changing I2C Address
    9. 5.9  Configuring Mask Settings
    10. 5.10 Exporting an NVM Configuration File
    11. 5.11 Loading a NVM Configuration File to PMIC
  9. 6NVM Programming
  10. 7Non-NVM Registers
  11. 8TPS6521405 default settings
  12.   A References

5.9 Configuring Mask Settings

There are several interrupt settings that can be masked to bypass specific PMIC monitoring features or modify how PMIC reacts when interrupts are detected. The interrupts that can be masked include undervoltage monitoring, temperature monitoring, among others. Figure 5-7 shows the mask settings in the configuration tab of the GUI.

Mask Settings in TPS65214-GUIFigure 5-8 Mask Settings in TPS65214-GUI
Table 5-18 MASK Settings on Register 0x1E
Register AddressBit
Bit#Field Name
0x1E7BYPASS_RV_FOR_RAIL_ENABLE

Table 5-19 MASK Settings on Register 0x1E
Register AddressBit
Bit#Field Name
0x247MASK_RETRY_COUNT
6B3_UV_MASK
5B2_UV_MASK
4B1_UV_MASK

2

LDO1_UV_MASK

1

LDO2_UV_MASK
Table 5-20 MASK Settings on Register 0x1E
Register AddressBit
Bit#Field Name
0x257MASK_INT_FOR_PB
6-5MASK_EFFECT
4MASK_INT_FOR_RV
3SENSOR_0_WARM_MASK
2SENSOR_1_WARM_MASK
1SENSOR_2_WARM_MASK