SLVAFW0 December   2025 TPS61381-Q1

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2TPS61381-Q1 Schematic Guideline
    1. 2.1 GND Connection
    2. 2.2 Driver Design
    3. 2.3 IO Configuration
    4. 2.4 Output Capacitor
    5. 2.5 Compensation Design
      1. 2.5.1 Small Signal Analysis
      2. 2.5.2 Step by Step Loop Compensation Design
  6. 3TPS61381-Q1 Layout Guide Line
    1. 3.1 Identification of the Critical Switching Loops
      1. 3.1.1 Low Side Driver Loop
      2. 3.1.2 Boost Leg Switching Loop
      3. 3.1.3 High Side Driver Loop
    2. 3.2 Power Component Placement
    3. 3.3 Layout Example
      1. 3.3.1 Optimizing Low Side Driver Loop Example
      2. 3.3.2 Optimizing Boost Leg Switching Loop Example
      3. 3.3.3 Optimizing High Side Driver Loop Example
      4. 3.3.4 Signal Circuit Routing Example
  7. 4Summary
  8. 5References

2.2 Driver Design

TPS61381-Q1 adjusts the driver speed by gate resistor (R5). While 1Ω is enough for most MOSFETs, apply a larger resistance (1-2Ω) if the Qgd is below 3nC.

TPS61381-Q1 Driver Design Figure 2-2 TPS61381-Q1 Driver Design

Do not apply less than 1Ω of resistance if the MOSFET has Qgd over 10nC. Slow driver speed can lead to lower efficiency and even power-FETs shooting-through.

R5 must withstand thermal heat generated by driver loss, so do not select a small package for R5. Driver loss can be calculated by:

Equation 1. P g l o s s = Q g V C C f s w

where VCC can be calculated as 5V.