SLVAFW0 December   2025 TPS61381-Q1

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2TPS61381-Q1 Schematic Guideline
    1. 2.1 GND Connection
    2. 2.2 Driver Design
    3. 2.3 IO Configuration
    4. 2.4 Output Capacitor
    5. 2.5 Compensation Design
      1. 2.5.1 Small Signal Analysis
      2. 2.5.2 Step by Step Loop Compensation Design
  6. 3TPS61381-Q1 Layout Guide Line
    1. 3.1 Identification of the Critical Switching Loops
      1. 3.1.1 Low Side Driver Loop
      2. 3.1.2 Boost Leg Switching Loop
      3. 3.1.3 High Side Driver Loop
    2. 3.2 Power Component Placement
    3. 3.3 Layout Example
      1. 3.3.1 Optimizing Low Side Driver Loop Example
      2. 3.3.2 Optimizing Boost Leg Switching Loop Example
      3. 3.3.3 Optimizing High Side Driver Loop Example
      4. 3.3.4 Signal Circuit Routing Example
  7. 4Summary
  8. 5References

2.4 Output Capacitor

TPS61381 needs at least 100uF local total output capacitance. TI recommends both MLCC and electrolytic capacitor placed in parallel

Electrolytic capacitors has large ESR and is ineffective for filtering high frequency ripple and switching noise. Make sure the MLCC effective capacitance at Boost Vout target is over 40uF. The MLCC capacitance needs further increase if the electrolytic capacitors has large ESR over 500mΩ. Note that ESR of electrolytic capacitor can increase by over 10 times under low temperature condition and can seriously affect loop stability. Make sure low temperature ESR is considered when calculating loop stability (View Section 2.5 for loop stability calculation).

TPS61381-Q1 Output Capacitor Figure 2-4 TPS61381-Q1 Output Capacitor

MLCCs has DC-bias derating that significantly reduce the effective capacitance when a DC-voltage is applied. Check the DC-bias curve at boost Vout target voltage when calculating the capacitance.