SLVAFW0 December   2025 TPS61381-Q1

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2TPS61381-Q1 Schematic Guideline
    1. 2.1 GND Connection
    2. 2.2 Driver Design
    3. 2.3 IO Configuration
    4. 2.4 Output Capacitor
    5. 2.5 Compensation Design
      1. 2.5.1 Small Signal Analysis
      2. 2.5.2 Step by Step Loop Compensation Design
  6. 3TPS61381-Q1 Layout Guide Line
    1. 3.1 Identification of the Critical Switching Loops
      1. 3.1.1 Low Side Driver Loop
      2. 3.1.2 Boost Leg Switching Loop
      3. 3.1.3 High Side Driver Loop
    2. 3.2 Power Component Placement
    3. 3.3 Layout Example
      1. 3.3.1 Optimizing Low Side Driver Loop Example
      2. 3.3.2 Optimizing Boost Leg Switching Loop Example
      3. 3.3.3 Optimizing High Side Driver Loop Example
      4. 3.3.4 Signal Circuit Routing Example
  7. 4Summary
  8. 5References

3.1.2 Boost Leg Switching Loop

Boost leg switching loop is the most critical loop for boost devices. Long and thin traces in these two loops can cause excessive noise, overshoot, and ring on the switch node, and the ground bounce because of the parasitic inductance. During a MOSFET switching event, the slew rate of the commutating current can exceed 3–5A/ns, so a 2nH parasitic inductance can result in a voltage spike of 6V. The pulsed current flowing in these critical loops during switching are rich in harmonic content and can cause a large radiated energy emission and electromagnetic interference issue if the loop area is not carefully minimized. This is crucial to minimize the trace length and the enclosed area of loop.

TPS61381-Q1 Boost Leg Switching Loop Figure 3-2 TPS61381-Q1 Boost Leg Switching Loop