SLVAFW0 December   2025 TPS61381-Q1

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2TPS61381-Q1 Schematic Guideline
    1. 2.1 GND Connection
    2. 2.2 Driver Design
    3. 2.3 IO Configuration
    4. 2.4 Output Capacitor
    5. 2.5 Compensation Design
      1. 2.5.1 Small Signal Analysis
      2. 2.5.2 Step by Step Loop Compensation Design
  6. 3TPS61381-Q1 Layout Guide Line
    1. 3.1 Identification of the Critical Switching Loops
      1. 3.1.1 Low Side Driver Loop
      2. 3.1.2 Boost Leg Switching Loop
      3. 3.1.3 High Side Driver Loop
    2. 3.2 Power Component Placement
    3. 3.3 Layout Example
      1. 3.3.1 Optimizing Low Side Driver Loop Example
      2. 3.3.2 Optimizing Boost Leg Switching Loop Example
      3. 3.3.3 Optimizing High Side Driver Loop Example
      4. 3.3.4 Signal Circuit Routing Example
  7. 4Summary
  8. 5References

3.3.4 Signal Circuit Routing Example

The area of the switching node SW and IL must be as small as possible. If the SW and IL are poured with big area copper planes, the high dv/dt noisy signal can couple into other traces nearby though capacitive coupling and causes electromagnetic interference issues. Signal traces must avoid the area near or under SW and IL nets.

TPS61381-Q1 Signal Circuit Routing Example Figure 3-8 TPS61381-Q1 Signal Circuit Routing Example

COMP pin is vulnerable to CM noise and the compensation parts must be placed near the IC to make sure the high frequency cap C8 can bypass the noise.