SLVAFW0 December   2025 TPS61381-Q1

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2TPS61381-Q1 Schematic Guideline
    1. 2.1 GND Connection
    2. 2.2 Driver Design
    3. 2.3 IO Configuration
    4. 2.4 Output Capacitor
    5. 2.5 Compensation Design
      1. 2.5.1 Small Signal Analysis
      2. 2.5.2 Step by Step Loop Compensation Design
  6. 3TPS61381-Q1 Layout Guide Line
    1. 3.1 Identification of the Critical Switching Loops
      1. 3.1.1 Low Side Driver Loop
      2. 3.1.2 Boost Leg Switching Loop
      3. 3.1.3 High Side Driver Loop
    2. 3.2 Power Component Placement
    3. 3.3 Layout Example
      1. 3.3.1 Optimizing Low Side Driver Loop Example
      2. 3.3.2 Optimizing Boost Leg Switching Loop Example
      3. 3.3.3 Optimizing High Side Driver Loop Example
      4. 3.3.4 Signal Circuit Routing Example
  7. 4Summary
  8. 5References

3.2 Power Component Placement

Figure 3-4 shows the placement of the power MOSFETs, input and output ceramic capacitors, main inductor, and the TPS61381-Q1 silicon on the top layer.

TPS61381-Q1 Power Component Placement Example Figure 3-4 TPS61381-Q1 Power Component Placement Example

Output capacitors are placed adjacent to the VOUT pin of the TPS61381 external MOSFET source. The main inductor L1 is placed near the IL pin. The IL and SW nodes are poured with small copper plane to reduce the capacitive coupling relating to the SW node high dv/dt transitions. A large SW node copper plane helps the thermal, but can cause severe radiated emissions.