SLVAFW0 December   2025 TPS61381-Q1

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2TPS61381-Q1 Schematic Guideline
    1. 2.1 GND Connection
    2. 2.2 Driver Design
    3. 2.3 IO Configuration
    4. 2.4 Output Capacitor
    5. 2.5 Compensation Design
      1. 2.5.1 Small Signal Analysis
      2. 2.5.2 Step by Step Loop Compensation Design
  6. 3TPS61381-Q1 Layout Guide Line
    1. 3.1 Identification of the Critical Switching Loops
      1. 3.1.1 Low Side Driver Loop
      2. 3.1.2 Boost Leg Switching Loop
      3. 3.1.3 High Side Driver Loop
    2. 3.2 Power Component Placement
    3. 3.3 Layout Example
      1. 3.3.1 Optimizing Low Side Driver Loop Example
      2. 3.3.2 Optimizing Boost Leg Switching Loop Example
      3. 3.3.3 Optimizing High Side Driver Loop Example
      4. 3.3.4 Signal Circuit Routing Example
  7. 4Summary
  8. 5References

2.5.1 Small Signal Analysis

The TPS61381-Q1 uses the fixed frequency peak current mode control with an internal adaptive slope compensation to avoid subharmonic oscillation. With the inductor current information sensed, the small-signal model of the power stage reduces from a two-pole system, created by L and COUT, to a single-pole system, created by ROUT and COUT. The single-pole system is easily used with the loop compensation. Figure 2-6 shows the equivalent small signal elements of a boost converter.

TPS61381-Q1 Control Equivalent Circuitry Model Figure 2-6 TPS61381-Q1 Control Equivalent Circuitry Model

The small signal of power stage can be shown by:

Equation 2. KPSs=Rout1-D2Rsense×1+s2π×fzESR1-s2π×fzRHP1+s2π×fpPS

Where:

  • D is the duty cycle
  • Rout is the output load resistance
  • Rsense is the equivalent internal current sense resistor, which is typically 6mΩ

The single pole of the power stage can be given by:

Equation 3. fpPS=22π×Cout×Rout

Where:

  • Cout is the output capacitance. For a boost converter having multiple identical output capacitors in parallel, simply combine the capacitors with the equivalent capacitance

The zero created by the ESR of the output capacitor can be given by:

Equation 4. fzESR=12π×Cout×RESR

Where:

  • RESR is the equivalent resistance in series of the output capacitor

The right-hand plane zero can be given by:

Equation 5. fzRHP=Rout(1-D)22π×L

Where:

  • D is the duty cycle
  • Rout is the output load resistor
  • L is the inductance

Equation 6 shows the equation for feedback resistor network and the compensation network.

Equation 6. HCOMPs=Gcomp×REA×Rup+RdownRdown×1+s2π×fzCOMPs1+s2π×fpCOMP11+s2π×fpCOMP2

Where:

  • GCOMP is the gain of the error amplifier, typically GEA = 24uS
  • REA is the output impedance of the error amplifier, typically REA = 5MΩ
  • ƒpCOMP1, ƒpCOMP2 is the pole's frequency of the compensation
  • fzCOMP is the zero’s frequency of the compensation network

ƒpCOMP1 can be given by:

Equation 7. fpCOMP1=12π×REA×CCOMP

Where:

  • CCOMP is the compensation capacitor

ƒpCOMP2 can be given by:

Equation 8. fpCOMP2=12π×RCOMP×CHF

Where:

  • CHF is the high frequency bypass capacitor on COMP pin
  • RCOMP is the resistor of the compensation network

ƒzCOMP can be given by:

Equation 9. fzCOMP=12π×RCOMP×CCOMP

Where:

  • CCOMP is the zero capacitor compensation
  • RCOMP is the resistor of the compensation network