SLVS348N July   2001  – January 2025 TPS793

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagrams
    3. 6.3 Feature Description
      1. 6.3.1 Undervoltage Lockout (UVLO)
      2. 6.3.2 Shutdown
      3. 6.3.3 Active Discharge (new chip)
      4. 6.3.4 Foldback Current Limit
      5. 6.3.5 Thermal Protection
      6. 6.3.6 Reverse Current
    4. 6.4 Device Functional Modes
      1. 6.4.1 Normal Operation
      2. 6.4.2 Dropout Operation
      3. 6.4.3 Disabled
  8. 7 Application and Implementation
    1. 7.1 Application Information
      1. 7.1.1 Adjustable Operation
      2. 7.1.2 Exiting Dropout
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1 Capacitor Recommendations
        2. 7.2.2.2 Input and Output Capacitor Requirements
        3. 7.2.2.3 Noise Reduction and Feed-Forward Capacitor Requirements
      3. 7.2.3 Application Curves
    3. 7.3 Best Design Practices
    4. 7.4 Power Supply Recommendations
    5. 7.5 Layout
      1. 7.5.1 Layout Guidelines
        1. 7.5.1.1 Board Layout Recommendations to Improve PSRR and Noise Performance
        2. 7.5.1.2 Power Dissipation
      2. 7.5.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 Development Support
        1. 8.1.1.1 Evaluation Modules
        2. 8.1.1.2 Spice Models
      2. 8.1.2 Device Nomenclature
    2. 8.2 Documentation Support
      1. 8.2.1 Related Documentation
    3. 8.3 Receiving Notification of Documentation Updates
    4. 8.4 Support Resources
    5. 8.5 Trademarks
    6. 8.6 Electrostatic Discharge Caution
    7. 8.7 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

4 Pin Configuration and Functions

TPS793 DBV Package,5-Pin SOT-23 Fixed Voltage Version(Top View)Figure 4-1 DBV Package,5-Pin SOT-23 Fixed Voltage Version(Top View)
TPS793 YZQ Package,5-Pin DSBGA(Top View) (Legacy Chip Only)Figure 4-3 YZQ Package,5-Pin DSBGA
(Top View) (Legacy Chip Only)
TPS793 DBV Package,6-Pin SOT-23 Adjustable Voltage Version(Top View)Figure 4-2 DBV Package,6-Pin SOT-23 Adjustable Voltage Version(Top View)
Table 4-1 Pin Functions
PIN I/O DESCRIPTION
NAME DBV YZQ
EN 3 A3 I Enable pin. Driving the enable pin (EN) high turns on the regulator. Driving this pin low puts the regulator into shutdown mode. EN can be connected to IN if not used.
FB 5 — I Feedback pin. This terminal is the feedback input pin for the adjustable device. Fixed voltage versions in the DBV package do not have this pin.
GND 2 A1 — Regulator ground.
IN 1 C3 I Input to the device.
NR/NC 4 B2 — Noise Reduction pin (legacy chip only). Connecting an external capacitor to this pin filters noise generated by the internal bandgap. This configuration improves power-supply rejection and reduces output noise for the legacy chip and YZQ package only.

No Connect pin (new chip only). This pin is not internally connected. Connect to GND for improved thermal performance or leave floating. For lower noise performance on a fixed device, consider looking at the TPS7A20.

OUT 6 C1 O Output of the regulator.