SLVSGS5A December   2023  – June 2024 DRV3946-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 SPI Timing Requirements
    7. 5.7 Timing Diagrams
    8. 5.8 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1  Recommended External Components
      2. 6.3.2  Power Supplies and Monitors
        1. 6.3.2.1 PVDD and VDD Power Supplies
        2. 6.3.2.2 PVDD Monitor
        3. 6.3.2.3 VDD Monitor
        4. 6.3.2.4 RESET (nPOR)
        5. 6.3.2.5 Device Safety Layer
      3. 6.3.3  Output Driver
        1. 6.3.3.1 Retry Wait
        2. 6.3.3.2 Over Current Protection
        3. 6.3.3.3 Thermal Protection
      4. 6.3.4  Start-up Sequencing
      5. 6.3.5  Current Control
        1. 6.3.5.1 Internal Regulation Mode
          1. 6.3.5.1.1 Current Thresholds
          2. 6.3.5.1.2 PWM Cycle Control
        2. 6.3.5.2 Fixed Frequency, Variable Duty Cycle Mode
        3. 6.3.5.3 Fixed Duty Cycle, Variable Frequency Mode
        4. 6.3.5.4 Quick Turn Off
        5. 6.3.5.5 PWM Frequency
        6. 6.3.5.6 Minimum and Maximum Duty Cycle
      6. 6.3.6  EN/EN1 and DIS/EN2 pins
      7. 6.3.7  Diagnostics Features
        1. 6.3.7.1 On State Diagnostics
          1. 6.3.7.1.1 PWM Cycle Warnings
          2. 6.3.7.1.2 Timer Based Warnings
        2. 6.3.7.2 Off-state Diagnostics
      8. 6.3.8  nFAULT/NAD Pin
      9. 6.3.9  Fault Table
      10. 6.3.10 Programming
        1. 6.3.10.1 SPI Interface
        2. 6.3.10.2 Addressable SPI
        3. 6.3.10.3 SPI Error Indicators
        4. 6.3.10.4 SPI Format
        5. 6.3.10.5 SPI Watchdog Monitor
  8. 7 Register Maps
    1. 7.1 STATUS Registers
      1. 7.1.1 STATUS0 Register (Address = 1h) [Reset = 2500h]
      2. 7.1.2 STATUS1 Register (Address = 2h) [Reset = 0803h]
      3. 7.1.3 STATUS2 Register (Address = 3h) [Reset = 0000h]
      4. 7.1.4 STATUS3 Register (Address = 4h) [Reset = 0000h]
      5. 7.1.5 STATUS4 Register (Address = Ah) [Reset = 0000h]
      6. 7.1.6 STATUS5 Register (Address = Bh) [Reset = 0000h]
    2. 7.2 MEAS Registers
      1. 7.2.1 MEAS0 Register (Address = 5h) [Reset = 0000h]
      2. 7.2.2 MEAS1 Register (Address = 6h) [Reset = 0000h]
      3. 7.2.3 MEAS2 Register (Address = 7h) [Reset = 0000h]
      4. 7.2.4 MEAS3 Register (Address = 8h) [Reset = 0000h]
      5. 7.2.5 MEAS4 Register (Address = 9h) [Reset = 0000h]
      6. 7.2.6 MEAS5 Register (Address = Ch) [Reset = 0000h]
      7. 7.2.7 MEAS6 Register (Address = Dh) [Reset = 0000h]
    3. 7.3 CONFIG A Registers
      1. 7.3.1 CONFIG_A0 Register (Address = 10h) [Reset = C040h]
      2. 7.3.2 CONFIG_A1 Register (Address = 11h) [Reset = C040h]
      3. 7.3.3 CONFIG_A2 Register (Address = 12h) [Reset = 2424h]
      4. 7.3.4 CONFIG_A3 Register (Address = 13h) [Reset = 0088h]
      5. 7.3.5 CONFIG_A4 Register (Address = 14h) [Reset = 130Ch]
      6. 7.3.6 CONFIG_A5 Register (Address = 15h) [Reset = 8000h]
      7. 7.3.7 CONFIG_A6 Register (Address = 16h) [Reset = 0000h]
    4. 7.4 CONFIG B Registers
      1. 7.4.1 CONFIG_B0 Register (Address = 17h) [Reset = 2623h]
      2. 7.4.2 CONFIG_B1 Register (Address = 18h) [Reset = 0040h]
      3. 7.4.3 CONFIG_B2 Register (Address = 19h) [Reset = 0B0Bh]
      4. 7.4.4 CONFIG_B3 Register (Address = 1Ah) [Reset = 8000h]
      5. 7.4.5 CONFIG_B4 Register (Address = 1Bh) [Reset = 0000h]
    5. 7.5 CMD Registers
      1. 7.5.1 CMD0 Register (Address = 1Ch) [Reset = 8000h]
      2. 7.5.2 CMD1 Register (Address = 1Dh) [Reset = 0000h]
      3. 7.5.3 CMD2 Register (Address = 1Eh) [Reset = 0000h]
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Transient Thermal Impedance and Current Capability
      3. 8.2.3 Application Performance Plots
      4. 8.2.4 PVDD Capacitance Value Estimation
    3. 8.3 Initialization Setup
      1. 8.3.1 Device Initialization – NAD
      2. 8.3.2 Device Initialization – Configuration
      3. 8.3.3 System Initialization
        1. 8.3.3.1 EN/EN1 and DIS/EN2 Function Check
        2. 8.3.3.2 nFAULT Signalling Check
        3. 8.3.3.3 Device Timing Check
        4. 8.3.3.4 Secondary Logic Check
      4. 8.3.4 Turn On Relay
      5. 8.3.5 Turn Off Relay
        1. 8.3.5.1 Using Target Device Command
        2. 8.3.5.2 Using Broadcast Command
    4. 8.4 Power Supply Recommendations
      1. 8.4.1 PVDD Supply Requirements
      2. 8.4.2 PVDD Undervoltage Transients - Contactor Chatter or Weld Prevention
    5. 8.5 Layout
      1. 8.5.1 Layout Guidelines
  10. 9 Device and Documentation Support
    1. 9.1 Receiving Notification of Documentation Updates
    2. 9.2 Support Resources
    3. 9.3 Trademarks
    4. 9.4 Electrostatic Discharge Caution
    5. 9.5 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information
    1. 11.1 Package Option Addendum
    2. 11.2 Tape and Reel Information

6.3.4 Start-up Sequencing

DRV3946-Q1 Simplified Start-up Sequencing DiagramFigure 6-3 Simplified Start-up Sequencing Diagram

  • Either PVDD or VDD will initiate power up of the device.

  • A release of the internal power-on-reset (nPOR on V5_S) moves the device into the INIT1 state. In INIT1, the factory programmed NVM is loaded and a memory BIST (CRC check) and digital BIST is performed.

    • If there is a BIST failure, the device will enter a locked error state indicated by driving the nFAULT pin low and DEV_ERR fault on the SPI (SDO output Hi-Z). Only a power cycle can re-start this sequence.

  • After entering the INIT1 STATE, the device waits until both VDD and PVDD are valid. For example, no VDD overvoltage, VDD undervoltage, or PVDD undervoltage before transitioning to the INIT2 state.

    • By default, the SPI SDO VDD_ERR is set. Only in case of no supply error, will VDD_ERR clear.

  • In the INIT2 STATE, NAD_ERR is set by default. The device will start the node address (NAD) determination based on the pull-up resistor on the nFAULT/NAD pin. After a valid NAD determination, the NAD_ERR will clear.

    • After a successful NAD determination, the SPI POR bit in STATUS0 is set to indicate a device wake up from reset, SPI communication is available, and nFAULT indicators are configured for default settings.

  • Next, an analog BIST (ABIST) is performed, whose failure is recorded in STARTUP_BIST_W bit in STATUS1.

  • The resistance on IPROPI is determined by forcing a current IRIPROPI on both the IPROPIx pins, whose failure is recorded in CHx_RIPROPI_W bit in STATUS1 register.

    • An internal resistor RINT used for secondary ripple loop current regulation is calibrated to match the resistance on the IPROPI pin, by forcing a current on the external resistor on the IPROPIx pin.

    • Voltage and resistance measured on IPROPIx pin are recorded in MEAS5 and MEAS6 resisters.

  • EN/EN1_PIN_STAT and DIS/EN2_PIN_STAT will reflect the instantaneous pin level.

  • If a NAD_ERR is detected after the automatic NAD determination, the microcontroller can either request a re-determination using the REINIT_NAD broadcast command or issue a NAD_OVERRIDE broadcast command with the ASSIGNED_NAD. Only the device(s) with the NAD_ERROR will process this command.

  • While in INIT2, if VDD overvoltage or undervoltage occurs, NAD determination can be wrong and NAD_ERR is set. RE_INIT_NAD command has to be sent once VDD_ERR is cleared.

  • VDD_ERR corresponds to VDD UV or OV or PVDD UV till device enters STANDBY.

  • To enter the STANDBY STATE, the device now expects the microcontroller to perform a series of steps -

    • Write 14 bytes of CONFIG A and 10 bytes of CONFIG B registers along with their calculated CRCs

    • Issue a CLR_FAULT SPI command. If there are no wanrnings, this command puts the device in the STANDBY state with nFAULT de-asserted.

  • Once in the STANDBY state, the device monitors the load with off-state diagnostics with nFAULT fault assertion as configured.

  • The EN/EN1 and DIS/EN2 pins must be driven AND the CHx_CTRL bits in CMD1 register must be programmed appropriately to turn ON the driver. These pins can be configured as ENABLE and DISABLE for both outputs (default) or as ENABLE1 and ENABLE2 for each output seperately.