SLVSGS5A December   2023  – June 2024 DRV3946-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 SPI Timing Requirements
    7. 5.7 Timing Diagrams
    8. 5.8 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1  Recommended External Components
      2. 6.3.2  Power Supplies and Monitors
        1. 6.3.2.1 PVDD and VDD Power Supplies
        2. 6.3.2.2 PVDD Monitor
        3. 6.3.2.3 VDD Monitor
        4. 6.3.2.4 RESET (nPOR)
        5. 6.3.2.5 Device Safety Layer
      3. 6.3.3  Output Driver
        1. 6.3.3.1 Retry Wait
        2. 6.3.3.2 Over Current Protection
        3. 6.3.3.3 Thermal Protection
      4. 6.3.4  Start-up Sequencing
      5. 6.3.5  Current Control
        1. 6.3.5.1 Internal Regulation Mode
          1. 6.3.5.1.1 Current Thresholds
          2. 6.3.5.1.2 PWM Cycle Control
        2. 6.3.5.2 Fixed Frequency, Variable Duty Cycle Mode
        3. 6.3.5.3 Fixed Duty Cycle, Variable Frequency Mode
        4. 6.3.5.4 Quick Turn Off
        5. 6.3.5.5 PWM Frequency
        6. 6.3.5.6 Minimum and Maximum Duty Cycle
      6. 6.3.6  EN/EN1 and DIS/EN2 pins
      7. 6.3.7  Diagnostics Features
        1. 6.3.7.1 On State Diagnostics
          1. 6.3.7.1.1 PWM Cycle Warnings
          2. 6.3.7.1.2 Timer Based Warnings
        2. 6.3.7.2 Off-state Diagnostics
      8. 6.3.8  nFAULT/NAD Pin
      9. 6.3.9  Fault Table
      10. 6.3.10 Programming
        1. 6.3.10.1 SPI Interface
        2. 6.3.10.2 Addressable SPI
        3. 6.3.10.3 SPI Error Indicators
        4. 6.3.10.4 SPI Format
        5. 6.3.10.5 SPI Watchdog Monitor
  8. 7 Register Maps
    1. 7.1 STATUS Registers
      1. 7.1.1 STATUS0 Register (Address = 1h) [Reset = 2500h]
      2. 7.1.2 STATUS1 Register (Address = 2h) [Reset = 0803h]
      3. 7.1.3 STATUS2 Register (Address = 3h) [Reset = 0000h]
      4. 7.1.4 STATUS3 Register (Address = 4h) [Reset = 0000h]
      5. 7.1.5 STATUS4 Register (Address = Ah) [Reset = 0000h]
      6. 7.1.6 STATUS5 Register (Address = Bh) [Reset = 0000h]
    2. 7.2 MEAS Registers
      1. 7.2.1 MEAS0 Register (Address = 5h) [Reset = 0000h]
      2. 7.2.2 MEAS1 Register (Address = 6h) [Reset = 0000h]
      3. 7.2.3 MEAS2 Register (Address = 7h) [Reset = 0000h]
      4. 7.2.4 MEAS3 Register (Address = 8h) [Reset = 0000h]
      5. 7.2.5 MEAS4 Register (Address = 9h) [Reset = 0000h]
      6. 7.2.6 MEAS5 Register (Address = Ch) [Reset = 0000h]
      7. 7.2.7 MEAS6 Register (Address = Dh) [Reset = 0000h]
    3. 7.3 CONFIG A Registers
      1. 7.3.1 CONFIG_A0 Register (Address = 10h) [Reset = C040h]
      2. 7.3.2 CONFIG_A1 Register (Address = 11h) [Reset = C040h]
      3. 7.3.3 CONFIG_A2 Register (Address = 12h) [Reset = 2424h]
      4. 7.3.4 CONFIG_A3 Register (Address = 13h) [Reset = 0088h]
      5. 7.3.5 CONFIG_A4 Register (Address = 14h) [Reset = 130Ch]
      6. 7.3.6 CONFIG_A5 Register (Address = 15h) [Reset = 8000h]
      7. 7.3.7 CONFIG_A6 Register (Address = 16h) [Reset = 0000h]
    4. 7.4 CONFIG B Registers
      1. 7.4.1 CONFIG_B0 Register (Address = 17h) [Reset = 2623h]
      2. 7.4.2 CONFIG_B1 Register (Address = 18h) [Reset = 0040h]
      3. 7.4.3 CONFIG_B2 Register (Address = 19h) [Reset = 0B0Bh]
      4. 7.4.4 CONFIG_B3 Register (Address = 1Ah) [Reset = 8000h]
      5. 7.4.5 CONFIG_B4 Register (Address = 1Bh) [Reset = 0000h]
    5. 7.5 CMD Registers
      1. 7.5.1 CMD0 Register (Address = 1Ch) [Reset = 8000h]
      2. 7.5.2 CMD1 Register (Address = 1Dh) [Reset = 0000h]
      3. 7.5.3 CMD2 Register (Address = 1Eh) [Reset = 0000h]
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Transient Thermal Impedance and Current Capability
      3. 8.2.3 Application Performance Plots
      4. 8.2.4 PVDD Capacitance Value Estimation
    3. 8.3 Initialization Setup
      1. 8.3.1 Device Initialization – NAD
      2. 8.3.2 Device Initialization – Configuration
      3. 8.3.3 System Initialization
        1. 8.3.3.1 EN/EN1 and DIS/EN2 Function Check
        2. 8.3.3.2 nFAULT Signalling Check
        3. 8.3.3.3 Device Timing Check
        4. 8.3.3.4 Secondary Logic Check
      4. 8.3.4 Turn On Relay
      5. 8.3.5 Turn Off Relay
        1. 8.3.5.1 Using Target Device Command
        2. 8.3.5.2 Using Broadcast Command
    4. 8.4 Power Supply Recommendations
      1. 8.4.1 PVDD Supply Requirements
      2. 8.4.2 PVDD Undervoltage Transients - Contactor Chatter or Weld Prevention
    5. 8.5 Layout
      1. 8.5.1 Layout Guidelines
  10. 9 Device and Documentation Support
    1. 9.1 Receiving Notification of Documentation Updates
    2. 9.2 Support Resources
    3. 9.3 Trademarks
    4. 9.4 Electrostatic Discharge Caution
    5. 9.5 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information
    1. 11.1 Package Option Addendum
    2. 11.2 Tape and Reel Information

7.4.1 CONFIG_B0 Register (Address = 17h) [Reset = 2623h]

CONFIG_B0 is shown in Table 7-42.

Return to the Summary Table.

Configuration register to setup the response to power supply overvoltage and undercurrent, forced wait duration, watchdog duration for SPI and off-state diagnostic comparator threshold setting.

Table 7-38 CONFIG_B0 Register Description
BitField

Type

ResetBit Description
15VDD_OV_SHUTOFF_EN

R/W

0x0Hi-Z driver when a VDD OV condition is detected
14RSVD

R

0x0

Reserved
13-11RETRY_WAIT_SELR/W0x4Forced wait duration between driver turn-off and turn-on retry, common for both outputs
10-9SPI_WD_SELR/W0x3Watchdog duration to detect any valid SPI read or write frames
8PC_REG_DISR/W0x0Disable current regulation during peak time (LS ON 100%)
7RSVD

R

0x0Reserved
6UCLO_ENR/W0x0Hi-Z driver when load under current condition is detected
5PVDD_OV_SHUTOFF_ENR/W

0x1

Hi-Z driver when a PVDD OV condition is detected
4SPI_WD_SHUTOFF_ENR/W0x0Hi-Z driver for a SPI watchdog violation
3OT_W_ACTIONR/W0x0Force SR_SEL = 0xF (max setting) when an OT_W is detected
2-0OLP_SELR/W0x3Off-state diagnostic (OLP) comparator threshold setting