SLVSGS5A December   2023  – June 2024 DRV3946-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 SPI Timing Requirements
    7. 5.7 Timing Diagrams
    8. 5.8 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1  Recommended External Components
      2. 6.3.2  Power Supplies and Monitors
        1. 6.3.2.1 PVDD and VDD Power Supplies
        2. 6.3.2.2 PVDD Monitor
        3. 6.3.2.3 VDD Monitor
        4. 6.3.2.4 RESET (nPOR)
        5. 6.3.2.5 Device Safety Layer
      3. 6.3.3  Output Driver
        1. 6.3.3.1 Retry Wait
        2. 6.3.3.2 Over Current Protection
        3. 6.3.3.3 Thermal Protection
      4. 6.3.4  Start-up Sequencing
      5. 6.3.5  Current Control
        1. 6.3.5.1 Internal Regulation Mode
          1. 6.3.5.1.1 Current Thresholds
          2. 6.3.5.1.2 PWM Cycle Control
        2. 6.3.5.2 Fixed Frequency, Variable Duty Cycle Mode
        3. 6.3.5.3 Fixed Duty Cycle, Variable Frequency Mode
        4. 6.3.5.4 Quick Turn Off
        5. 6.3.5.5 PWM Frequency
        6. 6.3.5.6 Minimum and Maximum Duty Cycle
      6. 6.3.6  EN/EN1 and DIS/EN2 pins
      7. 6.3.7  Diagnostics Features
        1. 6.3.7.1 On State Diagnostics
          1. 6.3.7.1.1 PWM Cycle Warnings
          2. 6.3.7.1.2 Timer Based Warnings
        2. 6.3.7.2 Off-state Diagnostics
      8. 6.3.8  nFAULT/NAD Pin
      9. 6.3.9  Fault Table
      10. 6.3.10 Programming
        1. 6.3.10.1 SPI Interface
        2. 6.3.10.2 Addressable SPI
        3. 6.3.10.3 SPI Error Indicators
        4. 6.3.10.4 SPI Format
        5. 6.3.10.5 SPI Watchdog Monitor
  8. 7 Register Maps
    1. 7.1 STATUS Registers
      1. 7.1.1 STATUS0 Register (Address = 1h) [Reset = 2500h]
      2. 7.1.2 STATUS1 Register (Address = 2h) [Reset = 0803h]
      3. 7.1.3 STATUS2 Register (Address = 3h) [Reset = 0000h]
      4. 7.1.4 STATUS3 Register (Address = 4h) [Reset = 0000h]
      5. 7.1.5 STATUS4 Register (Address = Ah) [Reset = 0000h]
      6. 7.1.6 STATUS5 Register (Address = Bh) [Reset = 0000h]
    2. 7.2 MEAS Registers
      1. 7.2.1 MEAS0 Register (Address = 5h) [Reset = 0000h]
      2. 7.2.2 MEAS1 Register (Address = 6h) [Reset = 0000h]
      3. 7.2.3 MEAS2 Register (Address = 7h) [Reset = 0000h]
      4. 7.2.4 MEAS3 Register (Address = 8h) [Reset = 0000h]
      5. 7.2.5 MEAS4 Register (Address = 9h) [Reset = 0000h]
      6. 7.2.6 MEAS5 Register (Address = Ch) [Reset = 0000h]
      7. 7.2.7 MEAS6 Register (Address = Dh) [Reset = 0000h]
    3. 7.3 CONFIG A Registers
      1. 7.3.1 CONFIG_A0 Register (Address = 10h) [Reset = C040h]
      2. 7.3.2 CONFIG_A1 Register (Address = 11h) [Reset = C040h]
      3. 7.3.3 CONFIG_A2 Register (Address = 12h) [Reset = 2424h]
      4. 7.3.4 CONFIG_A3 Register (Address = 13h) [Reset = 0088h]
      5. 7.3.5 CONFIG_A4 Register (Address = 14h) [Reset = 130Ch]
      6. 7.3.6 CONFIG_A5 Register (Address = 15h) [Reset = 8000h]
      7. 7.3.7 CONFIG_A6 Register (Address = 16h) [Reset = 0000h]
    4. 7.4 CONFIG B Registers
      1. 7.4.1 CONFIG_B0 Register (Address = 17h) [Reset = 2623h]
      2. 7.4.2 CONFIG_B1 Register (Address = 18h) [Reset = 0040h]
      3. 7.4.3 CONFIG_B2 Register (Address = 19h) [Reset = 0B0Bh]
      4. 7.4.4 CONFIG_B3 Register (Address = 1Ah) [Reset = 8000h]
      5. 7.4.5 CONFIG_B4 Register (Address = 1Bh) [Reset = 0000h]
    5. 7.5 CMD Registers
      1. 7.5.1 CMD0 Register (Address = 1Ch) [Reset = 8000h]
      2. 7.5.2 CMD1 Register (Address = 1Dh) [Reset = 0000h]
      3. 7.5.3 CMD2 Register (Address = 1Eh) [Reset = 0000h]
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Transient Thermal Impedance and Current Capability
      3. 8.2.3 Application Performance Plots
      4. 8.2.4 PVDD Capacitance Value Estimation
    3. 8.3 Initialization Setup
      1. 8.3.1 Device Initialization – NAD
      2. 8.3.2 Device Initialization – Configuration
      3. 8.3.3 System Initialization
        1. 8.3.3.1 EN/EN1 and DIS/EN2 Function Check
        2. 8.3.3.2 nFAULT Signalling Check
        3. 8.3.3.3 Device Timing Check
        4. 8.3.3.4 Secondary Logic Check
      4. 8.3.4 Turn On Relay
      5. 8.3.5 Turn Off Relay
        1. 8.3.5.1 Using Target Device Command
        2. 8.3.5.2 Using Broadcast Command
    4. 8.4 Power Supply Recommendations
      1. 8.4.1 PVDD Supply Requirements
      2. 8.4.2 PVDD Undervoltage Transients - Contactor Chatter or Weld Prevention
    5. 8.5 Layout
      1. 8.5.1 Layout Guidelines
  10. 9 Device and Documentation Support
    1. 9.1 Receiving Notification of Documentation Updates
    2. 9.2 Support Resources
    3. 9.3 Trademarks
    4. 9.4 Electrostatic Discharge Caution
    5. 9.5 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information
    1. 11.1 Package Option Addendum
    2. 11.2 Tape and Reel Information

7.1.1 STATUS0 Register (Address = 1h) [Reset = 2500h]

STATUS0 is shown in Table 7-8.

Return to the Summary Table.

Global status register including fault and warning summary indicators for device and output status. Also includes input pin status.

Table 7-8 STATUS0 Register Field Descriptions
BitField

Type

ResetBit DescriptionBit Enumerations
15-14NAD

R

0x0Device Node Address for SPI communication, determined based on pull-up resistor value on nFAULT/NAD pin

  • 0x0: NAD Address = 0

  • 0x1: NAD Address = 1

  • 0x2: NAD Address = 2

  • 0x3: NAD Address = 3

13POR

R

0x1

Power-on Reset indicator. Bit is latched during power up till CLR_FAULT command.
  • 0x0 = No POR
  • 0x1 = Prior POR event
12EN/EN1_PIN_STAT

R

0x0Transparent pin status indicator
  • 0x0 = Pin low
  • 0x1 = Pin high
11DIS/EN2_PIN_STAT

R

0x0

Transparent pin status indicator
  • 0x0 = Pin low
  • 0x1 = Pin high
10nFAULT_PIN_STAT

R

0x1

Transparent pin status indicator
  • 0x0 = Pin low (nFAULT asserted)
  • 0x1 = Pin high
9DEV_ERR

R

0x0

SDO response is Hi-Z in case of DEVICE_ERR. Device operation is disabled with outputs in Hi-Z. A power cycle (internal logic reset) is needed to clear this. This bit should always read low during operation.
8WARNINGS

R

0x1

Warning indicator (OR of warning bits in STATUS1 to STATUS5 registers). Read the other STATUS registers for the exact warning flag. Warnings flags are latched till CLR_FAULT command, but outputs are operational as commanded.
  • 0x0 = No warning
  • 0x1 = Warning indication
7CH1_OFF_DIAG_STAT

R

0x0

Output 1 off-state diagnostics status. In the event of a short to GND or OPEN detection, bit is latched till CLR_FAULT command.
  • 0x0 = Normal load
  • 0x1 = Loss of control (Short to GND or Open)
6-4CH1_STAT

R

0x0

Output 1 status. In the event of a shut off, output is locked out in Hi-Z and bit is latched till CLR_FAULT command.

  • 0x0 = Commanded OFF
  • 0x1 = Commanded ON, Normal operation
  • 0x2 = Commanded ON, Shut OFF due to TSD
  • 0x3 = Commanded ON, Shut OFF due to OCP_LS
  • 0x4 = Commanded ON, Shut OFF due to OCP_HS
  • 0x5 = Commanded ON, Shut OFF due to PVDD UV
  • 0x6 = Commanded ON, Shut OFF due to UCLO (Enabled by UCLO_EN)
  • 0x7 = Commanded ON, Shut OFF due to PVDD OV (Enabled by PVDD_OV_SHUTOFF_EN) or VDD OV (Enabled by VDD_OV_SHUTOFF_EN) or due to SPI WD (Enabled by SPI_WD_SHUTOFF_EN)
3CH2_OFF_DIAG_STAT

R

0x0

Output 2 off-state diagnostics status. In the event of a short to GND or OPEN detection, bit is latched till CLR_FAULT command.
  • 0x0 = Normal load
  • 0x1 = Loss of control (Short to GND or Open)
2-0CH2_STAT

R

0x0

Output 2 status. In the event of a shut off, output is locked out in Hi-Z and bit is latched till CLR_FAULT command.

  • 0x0 = Commanded OFF
  • 0x1 = Commanded ON, Normal operation
  • 0x2 = Commanded ON, Shut OFF due to TSD
  • 0x3 = Commanded ON, Shut OFF due to OCP_LS
  • 0x4 = Commanded ON, Shut OFF due to OCP_HS
  • 0x5 = Commanded ON, Shut OFF due to PVDD UV
  • 0x6 = Commanded ON, Shut OFF due to UCLO (Enabled by UCLO_EN)
  • 0x7 = Commanded ON, Shut OFF due to PVDD OV (Enabled by PVDD_OV_SHUTOFF_EN) or VDD OV (Enabled by VDD_OV_SHUTOFF_EN) or due to SPI WD (Enabled by SPI_WD_SHUTOFF_EN)