SLVSHH3A March   2025  – August 2025 DRV8263-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
    1. 5.1 HW Variant
    2. 5.2 SPI Variant
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Electrical Characteristics
    5. 6.5 Timing Requirements
    6. 6.6 Timing Diagrams
    7. 6.7 Thermal Information
      1. 6.7.1 Transient Thermal Impedance & Current Capability
    8. 6.8 Switching Waveforms
      1. 6.8.1 Output switching transients
        1. 6.8.1.1 High-Side Recirculation
      2. 6.8.2 Wake-up Transients
        1. 6.8.2.1 HW Variant
        2. 6.8.2.2 SPI Variant
      3. 6.8.3 Fault Reaction Transients
        1. 6.8.3.1 Retry setting
        2. 6.8.3.2 Latch setting
    9. 6.9 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 External Components
        1. 7.3.1.1 HW Variant
        2. 7.3.1.2 SPI Variant
      2. 7.3.2 Bridge Control
        1. 7.3.2.1 PH/EN mode
        2. 7.3.2.2 PWM mode
        3. 7.3.2.3 Independent mode
        4. 7.3.2.4 Register - Pin Control - SPI Variant Only
      3. 7.3.3 Device Configuration
        1. 7.3.3.1 Slew Rate (SR)
        2. 7.3.3.2 IPROPI
        3. 7.3.3.3 ITRIP Regulation
        4. 7.3.3.4 DIAG
          1. 7.3.3.4.1 HW variant
          2. 7.3.3.4.2 SPI variant
      4. 7.3.4 Protection and Diagnostics
        1. 7.3.4.1  Over Current Protection (OCP)
        2. 7.3.4.2  Over Temperature Warning (OTW) - SPI Variant Only
        3. 7.3.4.3  Over Temperature Protection (TSD)
        4. 7.3.4.4  Off-State Diagnostics (OLP)
        5. 7.3.4.5  On-State Diagnostics (OLA) - SPI Variant Only
        6. 7.3.4.6  VM Over Voltage Monitor - SPI Variant Only
        7. 7.3.4.7  VM Under Voltage Monitor
        8. 7.3.4.8  Power On Reset (POR)
        9. 7.3.4.9  Powered off Braking (POB)
        10. 7.3.4.10 Event Priority
      5. 7.3.5 Device Functional Modes
        1. 7.3.5.1 SLEEP State
        2. 7.3.5.2 STANDBY State
        3. 7.3.5.3 Wake-up to STANDBY State
        4. 7.3.5.4 ACTIVE State
        5. 7.3.5.5 nSLEEP Reset Pulse (HW Variant, LATCHED setting Only)
      6. 7.3.6 Programming - SPI Variant Only
        1. 7.3.6.1 Serial Peripheral Interface (SPI)
        2. 7.3.6.2 Standard Frame
        3. 7.3.6.3 SPI for Multiple Peripherals
          1. 7.3.6.3.1 Daisy Chain Frame for Multiple Peripherals
      7. 7.3.7 Register Map - SPI Variant Only
        1. 7.3.7.1 User Registers
  9. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Load Summary
    2. 8.2 Typical Application
      1. 8.2.1 HW Variant
      2. 8.2.2 SPI Variant
    3. 8.3 Power Supply Recommendations
      1. 8.3.1 Bulk Capacitance Sizing
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Device Support
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 Receiving Notification of Documentation Updates
    4. 9.4 Support Resources
    5. 9.5 Trademarks
    6. 9.6 Electrostatic Discharge Caution
    7. 9.7 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

7.3.4.4 Off-State Diagnostics (OLP)

The user can determine the impedance on the OUTx node using off-state diagnostics in the STANDBY state when the power FETs are off. With this diagnostics, detecting the following fault conditions passively in the STANDBY state is possible:

  • Output short to VM or GND
  • Open load for full-bridge load or low-side load
  • Open load for high-side load

Note: Detecting a load short with this diagnostic is not possible. However, the user can deduce this logically if an over-current fault (OCP) occurs during ACTIVE operation, but OLP diagnostics do not report any fault in the STANDBY state. The occurrence of both OCP in the ACTIVE state and OLP in the STANDBY state implies a terminal short (short on OUT node).

  • The user can configure the following combinations
    • Internal pull up resistor (ROLP_PU) on OUTx
    • Internal pull down resistor (ROLP_PD) on OUTx
    • Comparator reference level
    • Comparator input selection (OUT1 or OUT2)
  • This combination is determined by the controller inputs (pins only for the HW variant) or equivalent bits in the SPI_IN register for the SPI variant if the SPI_IN register has been unlocked.
  • HW variant - When off-state diagnostics are enabled, comparator output (OLP_CMP) is available on nFAULT pin.
  • SPI variant - The off-state diagnostics comparator output (OLP_CMP) is available on OLP_CMP bit in STATUS2 register. Additionally, if the SPI_IN register has been locked, this comparator output is also available on the nFAULT pin when off-state diagnostics are enabled.
  • The user is expected to toggle through all the combinations and record the comparator output after the output is settled.
  • Based on the input combinations and comparator output, the user can determine if there is a fault on the output.

DRV8263-Q1 Off-State Diagnostics for full-bridge Load (PH/EN or PWM Mode)Figure 7-5 Off-State Diagnostics for full-bridge Load (PH/EN or PWM Mode)

The OLP combinations and truth table for a no fault scenario vs. fault scenario for a full-bridge load in PH/EN or PWM modes is shown in Table 7-19.

Table 7-16 Off-State Diagnostics Table - PH/EN or PWM Mode (full-bridge)
User Inputs OLP Set-Up OLP CMP Output
nSLEEP DRVOFF EN/IN1 PH/IN2 OUT1 OUT2 CMP REF Output selected Normal Open GND Short VM Short
1 1 1 0 ROLP_PU ROLP_PD VOLP_REFH OUT1 L H L H
1 1 0 1 ROLP_PU ROLP_PD VOLP_REFL OUT2 H L L H
1 1 1 1 ROLP_PD ROLP_PU VOLP_REFL OUT2 H H L H

The OLP combinations and truth table for a no fault scenario vs. fault scenario for a low-side load in Independent mode is shown in Table 7-17.

Table 7-17 Off-State Diagnostics Table for Low-Side Load - Independent Mode
User Inputs OLP Set-Up OLP_CMP Output
DIAG pin S_DIAG bits nSLEEP DRVOFF EN/IN1 PH/IN2 OUT1 OUT2 CMP REF Output selected Normal Open Short to VM
LVL2, LVL6 01b 1 1 1 don't care ROLP_PU Hi-Z VOLP_REFH OUT1 L H H
LVL3, LVL4 11b 1 1 1 don't care ROLP_PD Hi-Z VOLP_REFL OUT1 L L H
LVL2, LVL6 01b 1 1 0 1 Hi-Z ROLP_PU VOLP_REFH OUT2 L H H
LVL3, LVL4 11b 1 1 0 1 Hi-Z ROLP_PD VOLP_REFL OUT2 L L H
The OLP combinations and truth table for a no fault scenario vs. fault scenario for a high-side load in Independent mode is shown in Table 7-18.
Table 7-18 Off-State Diagnostics Table for High-Side Load - Independent Mode
User Inputs OLP Set-Up OLP_CMP Output
DIAG pin S_DIAG bits nSLEEP DRVOFF EN/IN1 PH/IN2 OUT1 OUT2 CMP REF Output selected Normal Open Short to GND
LVL2, LVL6 01b 1 1 1 don't care ROLP_PU Hi-Z VOLP_REFH OUT1 H H L
LVL3, LVL4 11b 1 1 1 don't care ROLP_PD Hi-Z VOLP_REFL OUT1 H L L
LVL2, LVL6 01b 1 1 0 1 Hi-Z ROLP_PU VOLP_REFH OUT2 H H L
LVL3, LVL4 11b 1 1 0 1 Hi-Z ROLP_PD VOLP_REFL OUT2 H L L