SLVSHH3A March   2025  – August 2025 DRV8263-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
    1. 5.1 HW Variant
    2. 5.2 SPI Variant
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Electrical Characteristics
    5. 6.5 Timing Requirements
    6. 6.6 Timing Diagrams
    7. 6.7 Thermal Information
      1. 6.7.1 Transient Thermal Impedance & Current Capability
    8. 6.8 Switching Waveforms
      1. 6.8.1 Output switching transients
        1. 6.8.1.1 High-Side Recirculation
      2. 6.8.2 Wake-up Transients
        1. 6.8.2.1 HW Variant
        2. 6.8.2.2 SPI Variant
      3. 6.8.3 Fault Reaction Transients
        1. 6.8.3.1 Retry setting
        2. 6.8.3.2 Latch setting
    9. 6.9 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 External Components
        1. 7.3.1.1 HW Variant
        2. 7.3.1.2 SPI Variant
      2. 7.3.2 Bridge Control
        1. 7.3.2.1 PH/EN mode
        2. 7.3.2.2 PWM mode
        3. 7.3.2.3 Independent mode
        4. 7.3.2.4 Register - Pin Control - SPI Variant Only
      3. 7.3.3 Device Configuration
        1. 7.3.3.1 Slew Rate (SR)
        2. 7.3.3.2 IPROPI
        3. 7.3.3.3 ITRIP Regulation
        4. 7.3.3.4 DIAG
          1. 7.3.3.4.1 HW variant
          2. 7.3.3.4.2 SPI variant
      4. 7.3.4 Protection and Diagnostics
        1. 7.3.4.1  Over Current Protection (OCP)
        2. 7.3.4.2  Over Temperature Warning (OTW) - SPI Variant Only
        3. 7.3.4.3  Over Temperature Protection (TSD)
        4. 7.3.4.4  Off-State Diagnostics (OLP)
        5. 7.3.4.5  On-State Diagnostics (OLA) - SPI Variant Only
        6. 7.3.4.6  VM Over Voltage Monitor - SPI Variant Only
        7. 7.3.4.7  VM Under Voltage Monitor
        8. 7.3.4.8  Power On Reset (POR)
        9. 7.3.4.9  Powered off Braking (POB)
        10. 7.3.4.10 Event Priority
      5. 7.3.5 Device Functional Modes
        1. 7.3.5.1 SLEEP State
        2. 7.3.5.2 STANDBY State
        3. 7.3.5.3 Wake-up to STANDBY State
        4. 7.3.5.4 ACTIVE State
        5. 7.3.5.5 nSLEEP Reset Pulse (HW Variant, LATCHED setting Only)
      6. 7.3.6 Programming - SPI Variant Only
        1. 7.3.6.1 Serial Peripheral Interface (SPI)
        2. 7.3.6.2 Standard Frame
        3. 7.3.6.3 SPI for Multiple Peripherals
          1. 7.3.6.3.1 Daisy Chain Frame for Multiple Peripherals
      7. 7.3.7 Register Map - SPI Variant Only
        1. 7.3.7.1 User Registers
  9. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Load Summary
    2. 8.2 Typical Application
      1. 8.2.1 HW Variant
      2. 8.2.2 SPI Variant
    3. 8.3 Power Supply Recommendations
      1. 8.3.1 Bulk Capacitance Sizing
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Device Support
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 Receiving Notification of Documentation Updates
    4. 9.4 Support Resources
    5. 9.5 Trademarks
    6. 9.6 Electrostatic Discharge Caution
    7. 9.7 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

6.8.2.1 HW Variant

DRV8263-Q1 Wake-up from SLEEP State to STANDBY State without ACK Pulse Figure 6-3 Wake-up from SLEEP State to STANDBY State without ACK Pulse

Hand shake between controller and device during wake-up as follows:

  • t0: Controller - nSLEEP asserted high to initiate device wake-up
  • t1: Device internal state - Wake-up command registered by device (end of Sleep state)
  • t2: Device – nFAULT asserted low to acknowledge wake-up and indicate device ready for communication
  • t3: Device internal state - Initialization complete. nFAULT de-asserted. Device in STANDBY state.

DRV8263-Q1 Wake-up from SLEEP State to STANDBY State with ACK pulse Figure 6-4 Wake-up from SLEEP State to STANDBY State with ACK pulse

Hand shake between controller and device during wake-up as follows:

  • t0: Controller - nSLEEP asserted high to initiate device wake-up
  • t1: Device internal state - Wake-up command registered by device (end of Sleep state)
  • t2: Device – nFAULT asserted low to acknowledge wake-up and indicate device ready for communication
  • t3: Device internal state - Initialization complete
  • t4 (any time after t3): Controller – Issue nSLEEP reset pulse to acknowledge device wake-up
  • t5: Device - nFAULT de-asserted as an acknowledgment of nSLEEP reset pulse. Device in STANDBY state.

DRV8263-Q1 Power-up Via VDD to STANDBY State Without ACK Pulse Figure 6-5 Power-up Via VDD to STANDBY State Without ACK Pulse

Hand shake between controller and device during power-up as follows:

  • t0: Device internal state - POR asserted based on under voltage on VDD (external supply)
  • t1: Device internal state – POR de-asserted based on recovery of voltage on VDD (external supply)
  • t2: Device – nFAULT asserted low to acknowledge wake-up and indicate device ready for communication
  • t3: Device internal state - Initialization complete. nFAULT de-asserted. Device in STANDBY state.
DRV8263-Q1 Power-up via VDD to STANDBY State with ACK pulse Figure 6-6 Power-up via VDD to STANDBY State with ACK pulse

Hand shake between controller and device during power-up as follows:

  • t0: Device internal state - POR asserted based on under voltage on VDD (external supply)
  • t1: Device internal state – POR de-asserted based on recovery of voltage on VDD (external supply)
  • t2: Device – nFAULT asserted low to acknowledge wake-up and indicate device ready for communication
  • t3: Device internal state - Initialization complete
  • t4 (any time after t3): Controller – Issue nSLEEP reset pulse to acknowledge device power-up
  • t5: Device - nFAULT de-asserted as an acknowledgment of nSLEEP reset pulse. Device in STANDBY state.