SLVSHH3A March   2025  – August 2025 DRV8263-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
    1. 5.1 HW Variant
    2. 5.2 SPI Variant
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Electrical Characteristics
    5. 6.5 Timing Requirements
    6. 6.6 Timing Diagrams
    7. 6.7 Thermal Information
      1. 6.7.1 Transient Thermal Impedance & Current Capability
    8. 6.8 Switching Waveforms
      1. 6.8.1 Output switching transients
        1. 6.8.1.1 High-Side Recirculation
      2. 6.8.2 Wake-up Transients
        1. 6.8.2.1 HW Variant
        2. 6.8.2.2 SPI Variant
      3. 6.8.3 Fault Reaction Transients
        1. 6.8.3.1 Retry setting
        2. 6.8.3.2 Latch setting
    9. 6.9 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 External Components
        1. 7.3.1.1 HW Variant
        2. 7.3.1.2 SPI Variant
      2. 7.3.2 Bridge Control
        1. 7.3.2.1 PH/EN mode
        2. 7.3.2.2 PWM mode
        3. 7.3.2.3 Independent mode
        4. 7.3.2.4 Register - Pin Control - SPI Variant Only
      3. 7.3.3 Device Configuration
        1. 7.3.3.1 Slew Rate (SR)
        2. 7.3.3.2 IPROPI
        3. 7.3.3.3 ITRIP Regulation
        4. 7.3.3.4 DIAG
          1. 7.3.3.4.1 HW variant
          2. 7.3.3.4.2 SPI variant
      4. 7.3.4 Protection and Diagnostics
        1. 7.3.4.1  Over Current Protection (OCP)
        2. 7.3.4.2  Over Temperature Warning (OTW) - SPI Variant Only
        3. 7.3.4.3  Over Temperature Protection (TSD)
        4. 7.3.4.4  Off-State Diagnostics (OLP)
        5. 7.3.4.5  On-State Diagnostics (OLA) - SPI Variant Only
        6. 7.3.4.6  VM Over Voltage Monitor - SPI Variant Only
        7. 7.3.4.7  VM Under Voltage Monitor
        8. 7.3.4.8  Power On Reset (POR)
        9. 7.3.4.9  Powered off Braking (POB)
        10. 7.3.4.10 Event Priority
      5. 7.3.5 Device Functional Modes
        1. 7.3.5.1 SLEEP State
        2. 7.3.5.2 STANDBY State
        3. 7.3.5.3 Wake-up to STANDBY State
        4. 7.3.5.4 ACTIVE State
        5. 7.3.5.5 nSLEEP Reset Pulse (HW Variant, LATCHED setting Only)
      6. 7.3.6 Programming - SPI Variant Only
        1. 7.3.6.1 Serial Peripheral Interface (SPI)
        2. 7.3.6.2 Standard Frame
        3. 7.3.6.3 SPI for Multiple Peripherals
          1. 7.3.6.3.1 Daisy Chain Frame for Multiple Peripherals
      7. 7.3.7 Register Map - SPI Variant Only
        1. 7.3.7.1 User Registers
  9. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Load Summary
    2. 8.2 Typical Application
      1. 8.2.1 HW Variant
      2. 8.2.2 SPI Variant
    3. 8.3 Power Supply Recommendations
      1. 8.3.1 Bulk Capacitance Sizing
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Device Support
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 Receiving Notification of Documentation Updates
    4. 9.4 Support Resources
    5. 9.5 Trademarks
    6. 9.6 Electrostatic Discharge Caution
    7. 9.7 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

7.3.2.3 Independent mode

In this mode, the two half-bridges are configured to be used as two independent half-bridges. The Table 7-7 shows the logic table for bridge control.

Table 7-7 Control table - Independent mode
nSLEEP DRVOFF EN/IN1 PH/IN2 OUT1 OUT2 Device State
0 X X X Hi-Z Hi-Z SLEEP
1 1 0 0 Hi-Z Hi-Z STANDBY
1 1 1 0 Refer Off-state diagnostics table STANDBY
1 1 0 1 STANDBY
1 1 1 1 STANDBY
1 0 0 0 L L ACTIVE
1 0 0 1 L H(1) ACTIVE
1 0 1 0 H(1) L ACTIVE
1 0 1 1 H(1) H(1) ACTIVE

For the SPI variant, it is possible to have independent Hi-Z control of both half-bridges through equivalent bits, S_DRVOFF & S_DRVOFF2 in the SPI_IN register, when the SPI_IN register has been unlocked. Table 7-8 shows the logic table for bridge control using the pin & register combined inputs. Refer to - Register - Pin control for details on the combined inputs shown in Table 7-8.

Table 7-8 Control table - Independent mode for SPI variant, when SPI_IN is unlocked
nSLEEP DRVOFF1 combined DRVOFF2 combined EN_IN1 combined PH_IN2 combined OUT1 OUT2 Device State
0 X X X X Hi-Z Hi-Z SLEEP
1 1 1 0 0 Hi-Z Hi-Z STANDBY
1 1 1 1 0 Refer Off-state diagnostics table STANDBY
1 1 1 0 1 STANDBY
1 1 1 1 1 STANDBY
1 1 0 X 0 Hi-Z L ACTIVE
1 1 0 X 1 Hi-Z H(1) ACTIVE
1 0 1 0 X L Hi-Z ACTIVE
1 0 1 1 X H(1) Hi-Z ACTIVE
1 0 0 0 0 L L ACTIVE
1 0 0 0 1 L H(1) ACTIVE
1 0 0 1 0 H(1) L ACTIVE
1 0 0 1 1 H(1) H(1) ACTIVE
(1) Current sourcing out of device (VM → OUTx → Load)
(1) If internal ITRIP regulation is enabled and ITRIP level is reached, then OUTx is forced "L" for a fixed time

In this mode, the device behavior is as listed below:

  • Load current can be sensed only for current from VM → OUTx → Load. So current sense is not possible for high-side loads.
  • For the SPI variant, the current on IPROPI pin can be configured to be the current of either half-bridge or the sum of the high-side sense current from both the half-bridges, as per the ISEL bits.

  • For the HW variant, the current on IPROPI pin is the sum of the high-side sense current from both the half-bridges. This limits the ITRIP current regulation feature as a combined current regulation, rather than as truly independent.

  • Slew rate configurability is limited for low-side recirculation (low-side loads)
  • Active state open load diagnostics (OLA) is possible only for high-side loads
  • For the HW variant, it is NOT possible to have independent Hi-Z control of each half-bridge. Asserting DRVOFF pin high will Hi-Z both the half-bridges.