SLVUC32B June   2021  – February 2022 DRA829V , TDA4VM , TDA4VM-Q1 , TPS6594-Q1

 

  1.   Trademarks
  2. 1Introduction
  3. 2Device Versions
  4. 3Processor Connections
    1. 3.1 Power Mapping
    2. 3.2 Control Mapping
  5. 4Supporting Functional Safety Systems
    1. 4.1 Achieving ASIL-B System Requirements
    2. 4.2 Achieving up to ASIL-D System Requirements
  6. 5Static NVM Settings
    1. 5.1  Application-Based Configuration Settings
    2. 5.2  Device Identification Settings
    3. 5.3  BUCK Settings
    4. 5.4  LDO Settings
    5. 5.5  VCCA Settings
    6. 5.6  GPIO Settings
    7. 5.7  Finite State Machine (FSM) Settings
    8. 5.8  Interrupt Settings
    9. 5.9  POWERGOOD Settings
    10. 5.10 Miscellaneous Settings
    11. 5.11 Interface Settings
    12. 5.12 Multi-Device Settings
    13. 5.13 Watchdog Settings
  7. 6Pre-Configurable Finite State Machine (PFSM) Settings
    1. 6.1 Configured States
    2. 6.2 PFSM Triggers
    3. 6.3 Power Sequences
      1. 6.3.1 TO_SAFE_SEVERE and TO_SAFE
      2. 6.3.2 TO_SAFE_ORDERLY and TO_STANDBY
      3. 6.3.3 ACTIVE_TO_WARM
      4. 6.3.4 ESM_SOC_ERROR
      5. 6.3.5 PWR_SOC_ERROR
      6. 6.3.6 MCU_TO_WARM
      7. 6.3.7 TO_MCU
      8. 6.3.8 TO_ACTIVE
      9. 6.3.9 To Suspend-to-RAM (TO_S2R)
  8. 7Impact of NVM Changes
  9. 8References
  10. 9Revision History

6.1 Configured States

In this PDN, the PMIC devices have the following four configured power states:

  • Standby
  • Active
  • MCU Only
  • Suspend-to-RAM

In Figure 6-1, the configured PDN power states are shown, along with the transition conditions to move between the states. Additionally, the transitions to hardware states, such as SAFE RECOVERY and LP_STANDBY are shown. The hardware states are part of the Fixed Device Power Finite State Machine (FSM) and described in the TPS6594-Q1 data sheet, see Section 8.

GUID-D12EE20A-6A2B-4B1C-A83C-4B5F2E158E90-low.gif Figure 6-1 Pre-Configurable Mission Finite State Machine (PFSM) States and Transitions

When the PMICs transition from the FSM to the PFSM, several initialization instructions are performed to disable the residual voltage checks on both the BUCK and LDO regulators and set the FIRST_STARTUP_DONE bit. After these instructions are executed the PMICs wait for a valid ON Request (SU_ACTIVE trigger) before entering the ACTIVE state. The definition for each power state is described below:

    STANDBY The PMICs are powered by a valid supply on the system power rail (VCCA > VCCA_UV). All device resources are powered down in the STANDBY state. EN_DRV is forced low in this state. The processor is in the Off state, no voltage domains are energized. Refer to the Section 6.3.2 sequence description.
    ACTIVE The PMICs are powered by a valid supply. The PMICs are fully functional and supply power to all PDN loads. The processor has completed a recommended power up sequence with all voltage domains energized in both MCU and Main processor sections. Refer to the Section 6.3.8 sequence description.
    MCU ONLY The PMICs are powered by a valid supply. Only the power resources assigned to the processor MCU rails are on. Refer to the Section 6.3.7 sequence description. A special case of the MCU ONLY mode is when the state is entered due to an SOC power error. In this case the, the PMICs cannot transition to the ACTIVE or other states until the PMICs are intentionally moved to the MCU ONLY state by the processor. After this triggering of the TO_MCU sequence and 'reentery' into the MCU ONLY state can the PMICs transition back to the ACTIVE state.
    Suspend-to-RAM (S2R) The PMICs are powered by a valid supply. Only 3 SoC voltage domains (vdds_ddr_bias, vdds_ddr, and vdds_ddr_c) remain energized while all other domains are off to minimize total system power. EN_DRV is forced low in this state. Refer to the Section 6.3.9 sequence description.