SLVUD17B February 2025 – November 2025
Register settings can be changed on the Device Configuration Page and follow the register write mode specified on the Register Map page (Immediate or Deferred).
The BUCK & LDO Config tab holds register settings for each power rail of the PMIC. For more information on the Load Switch and BYPASS modes for the LDOs, refer to the TPS65214 Integrated Power Management IC for ARM Cortex Processors data sheet.
The Digital Pins Config tab is used to control settings for the enable configuration and digital I/O pins. For details on multi-function pins, see the TPS65214 Integrated Power Management IC for ARM Cortex Processors data sheet.
The Mask Config tab allows the user to control fault reporting for PMIC protection features which includes masking for undervoltage, temperature, and interrupt signals.
The Monitor PMIC Status tab holds a collection of read-only status registers that show the power rail enables and interrupts, which are displayed as digital LEDs. This section provides fast visual feedback on the PMIC and the operating conditions.