SLVUD67 September   2025 TPS6521505-Q1

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2Hardware Requirements for NVM Programming
  6. 3Typical NVM Flow
  7. 4TPS65215 with TPS65219EVM
  8. 5Programming Instructions
    1. 5.1  Configuring Enable Settings
    2. 5.2  Configuring the Bucks
    3. 5.3  Configuring LDOs
    4. 5.4  Configuring GPIOs
    5. 5.5  Configuring Sequence
    6. 5.6  Configuring Multi-Function Pins
    7. 5.7  Configuring the EN/PB/VSENSE Pin
    8. 5.8  Changing I2C Address
    9. 5.9  Configuring Mask Settings
    10. 5.10 NVM Re-Programming
  9.   A Non-NVM Registers
  10.   B Loading a NVM Configuration File to PMIC
  11.   C PMIC Configurable Fields
  12.   References
  13.   E Revision History

5.7 Configuring the EN/PB/VSENSE Pin

The enable pin of the PMIC can be configured as Enable, Push-Button, or VSENSE. In addition to the function, the deglitch can also be configured. Additionally, this pin has the option for first supply detection (FSD) to ignore the state of the EN/PB/VSENSE pin during the first power-up.

  • Figure 5-9 shows the settings to be changed when using the TPS65215-GUI.
  • Table 5-17 show the register fields to be written when NOT using the TPS65215-GUI.
EN/PB/VSENSE Configuration Using the TPS65215-GUI Figure 5-9 EN/PB/VSENSE Configuration Using the TPS65215-GUI
Table 5-17 NVM Registers for EN / PB / VSENSE
Register Address Bit Field Name Settings
First Supply Detection 0x20 7 PU_ON_FSD 0h = FSD Disabled
1h = FSD Enabled
Pin Configuration 5-4 EN_PB_VSENSE_CONFIG 0h = Enable
1h = Push Button
2h = VSENSE
3h = Enable
Deglitch 3 EN_PB_VSENSE_DEGL See the register map on the device-specific data sheet.