SLVUD67 September   2025 TPS6521505-Q1

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2Hardware Requirements for NVM Programming
  6. 3Typical NVM Flow
  7. 4TPS65215 with TPS65219EVM
  8. 5Programming Instructions
    1. 5.1  Configuring Enable Settings
    2. 5.2  Configuring the Bucks
    3. 5.3  Configuring LDOs
    4. 5.4  Configuring GPIOs
    5. 5.5  Configuring Sequence
    6. 5.6  Configuring Multi-Function Pins
    7. 5.7  Configuring the EN/PB/VSENSE Pin
    8. 5.8  Changing I2C Address
    9. 5.9  Configuring Mask Settings
    10. 5.10 NVM Re-Programming
  9.   A Non-NVM Registers
  10.   B Loading a NVM Configuration File to PMIC
  11.   C PMIC Configurable Fields
  12.   References
  13.   E Revision History

5.1 Configuring Enable Settings

The PMIC has an Active and Standby state where rails can be enabled or disabled. The state change can be triggered by the MODE/STBY pin when configured as STBY.

  • Figure 5-2 shows the settings to be changed when using the TPS65215-GUI.
  • Table 5-2 show the register fields to be written when NOT using the TPS65215-GUI.
Enable Settings Using the TPS65215-GUI Figure 5-2 Enable Settings Using the TPS65215-GUI
Table 5-1 NVM Registers for Enable Settings
Register Address Bit Field Name Settings
Enable rails in Active state 0x02 5 LDO2_EN 0h = Disabled
1h = Enabled
3 LDO1_EN 0h = Disabled
1h = Enabled
2 BUCK3_EN 0h = Disabled
1h = Enabled
1 BUCK2_EN 0h = Disabled
1h = Enabled
0 BUCK1_EN 0h = Disabled
1h = Enabled
Enable rails in Standby state 0x21 5 LDO2_STBY_EN 0h = Disabled
1h = Enabled
3 LDO1_STBY_EN 0h = Disabled
1h = Enabled
2 BUCK3_STBY_EN 0h = Disabled
1h = Enabled
1 BUCK2_STBY_EN 0h = Disabled
1h = Enabled
0 BUCK1_STBY_EN 0h = Disabled
1h = Enabled