SLVUD67 September   2025 TPS6521505-Q1

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2Hardware Requirements for NVM Programming
  6. 3Typical NVM Flow
  7. 4TPS65215 with TPS65219EVM
  8. 5Programming Instructions
    1. 5.1  Configuring Enable Settings
    2. 5.2  Configuring the Bucks
    3. 5.3  Configuring LDOs
    4. 5.4  Configuring GPIOs
    5. 5.5  Configuring Sequence
    6. 5.6  Configuring Multi-Function Pins
    7. 5.7  Configuring the EN/PB/VSENSE Pin
    8. 5.8  Changing I2C Address
    9. 5.9  Configuring Mask Settings
    10. 5.10 NVM Re-Programming
  9.   A Non-NVM Registers
  10.   B Loading a NVM Configuration File to PMIC
  11.   C PMIC Configurable Fields
  12.   References
  13.   E Revision History

5.6 Configuring Multi-Function Pins

The TPS65215 PMIC has three configurable multi-function pins. MODE/STBY and MODE/RESET can be configured as MODE to select the switching, as STBY to trigger a transition to Standby state, or as RESET to trigger a cold or warm reset. The VSEL_SD/VSEL_DDR pin can be configured to set the output voltage on LDO1 or to set the output voltage on Buck3. For information on pin polarity, see the device-specific data sheet.

Note: If VSEL_SD/VSEL_DDR is not used to set the output voltage on LDO1, then it must be configured as DDR and pulled to GND with a pull-down resistor in the schematic. Additionally, VSEL_SD_I2C_CTRL must be programmed to 1h.

  • Figure 5-6 shows the settings to be changed when using the TPS65215-GUI
  • Figure 5-8 show the register fields to be written when NOT using the TPS65215-GUI.
Multi-Function Configuration Using the TPS65215-GUI Figure 5-8 Multi-Function Configuration Using the TPS65215-GUI
Table 5-14 NVM Registers for VSEL_SD / VSEL_DDR
Register Address Bit Field Name Settings
Pin Function 0x1F 0 VSEL_DDR_SD 0h = VSEL pin configured as DDR to set the voltage on Buck3
1h = VSEL pin configured as SD to set the voltage on the VSEL_RAIL
Pin polarity 1 VSEL_SD_POLARITY 0h =
  • LOW: 1.8V
  • HIGH: LDOx_VOUT register

1h =
  • HIGH: 1.8V
  • LOW: LDOx_VOUT register
Table 5-15 NVM Registers for MODE / STBY
Register Address Bit Field Name Settings
Pin Function 0x20 1-0 MODE_STBY_CONFIG 0h = MODE
1h = STBY
2h = MODE and STBY
3h = MODE
Pin Polarity 0x1F 4 MODE_STBY_POLARITY For more information, see the Register Map in the device-specific data sheet.
Table 5-16 NVM Registers for MODE / RESET
Register Address Bit Field Name Settings
Pin Function 0x20 2 MODE_RESET_CONFIG 0h = MODE
1h = RESET
RESET config 6 WARM_COLD_RESET_CONFIG 0h = COLD RESET
1h = WARM RESET
Pin Polarity 0x1F 5 MODE_RESET_POLARITY For more information, see the Register Map in the device-specific data sheet.